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公开(公告)号：US20140354729A1
公开(公告)日：2014-12-04
申请号：US14123799
申请日：2011-07-01
IPC分类号： B41J2/045
CPC分类号： B41J2/04563 , B41J2/04528 , B41J2/0458 , B41J2/04588 , B41J2/04596 , B41J2/195
摘要： An apparatus including an analog memory, a temperature sensor, a comparator, and a pulse circuit. The analog memory is charged to a reference voltage corresponding to a predetermined temperature of a printhead. The temperature sensor measures a thermal voltage of at least one of the plurality of local areas of the printhead. The comparator obtains a comparison result by comparing the reference voltage to the thermal voltage. The pulse circuit selectively transmits a series of warming pulses to the at least one of the plurality of local areas of the printhead based on the comparison result.
摘要翻译： 一种包括模拟存储器，温度传感器，比较器和脉冲电路的装置。 模拟存储器被充电到对应于打印头的预定温度的参考电压。 温度传感器测量打印头的多个局部区域中的至少一个的热电压。 比较器通过将参考电压与热电压进行比较来获得比较结果。 基于比较结果，脉冲电路选择性地将一系列加温脉冲发送到打印头的多个局部区域中的至少一个。
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公开(公告)号：US08757778B2
公开(公告)日：2014-06-24
申请号：US13460322
申请日：2012-04-30
申请人： Peter Fricke , Mark Hunter
发明人： Peter Fricke , Mark Hunter
IPC分类号： B41J2/05
CPC分类号： B41J2/04541 , B41J2/04548 , B41J2/0458
摘要： Electronic circuitry compensates for variations or sags in electrical voltage within a thermal ink-jetting (TIJ) printing apparatus. Ground potential and other supply-related voltages are monitored and corresponding signals are provided. The signals are used, directly or by other circuitry, to affect the biasing of one or more transistors coupling TIJ resistors to supply voltage or ground nodes. Printing errors and related problems associated with voltage variations are reduced or eliminated accordingly.
摘要翻译： 电子电路补偿热喷墨（TIJ）打印设备内的电压变化或下降。 监测接地电位和其他电源相关电压，并提供相应的信号。 这些信号直接或由其他电路用于影响将TIJ电阻耦合到电源电压或接地节点的一个或多个晶体管的偏置。 相应地降低或消除了与电压变化相关的打印错误和相关问题。
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公开(公告)号：US20130286103A1
公开(公告)日：2013-10-31
申请号：US13460322
申请日：2012-04-30
申请人： Peter Fricke , Mark Hunter
发明人： Peter Fricke , Mark Hunter
CPC分类号： B41J2/04541 , B41J2/04548 , B41J2/0458
摘要： Electronic circuitry compensates for variations or sags in electrical voltage within a thermal ink-jetting (TIJ) printing apparatus. Ground potential and other supply-related voltages are monitored and corresponding signals are provided. The signals are used, directly or by other circuitry, to affect the biasing of one or more transistors coupling TIJ resistors to supply voltage or ground nodes. Printing errors and related problems associated with voltage variations are reduced or eliminated accordingly.
摘要翻译： 电子电路补偿热喷墨（TIJ）打印设备内的电压变化或下降。 监测接地电位和其他电源相关电压，并提供相应的信号。 这些信号直接或由其他电路用于影响将TIJ电阻耦合到电源电压或接地节点的一个或多个晶体管的偏置。 相应地降低或消除了与电压变化相关的打印错误和相关问题。
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4.发明申请Methods and memory structures using tunnel-junction device as control element 失效使用隧道结装置作为控制元件的方法和记忆结构公开(公告)号：US20060262627A1
公开(公告)日：2006-11-23
申请号：US11494397
申请日：2006-07-26
IPC分类号： G11C17/18
CPC分类号： G11C13/003 , G11C17/16 , G11C17/18 , G11C2213/76
摘要： A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A reference element comprising a tunnel-junction device may be used with a current source to fuse a memory storage element without fusing a tunnel-junction device of an associated control element. Methods of making the memory structure and using it in electronic devices are disclosed.
摘要翻译： 存储器结构包括电耦合到控制元件的存储器存储元件。 控制元件包括隧道连接装置。 存储器存储元件还可以包括隧道连接装置。 公开了一种用于熔接存储器存储元件的隧道结器件而不熔接相关控制元件的隧道结器件的方法。 存储器存储元件可以具有大于控制元件的有效横截面面积的有效横截面面积。 包括隧道结结器件的参考元件可以与电流源一起使用，以熔化存储器存储元件而不熔合相关联的控制元件的隧道连接器件。 公开了在电子设备中制作存储器结构并将其使用的方法。
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公开(公告)号：US07130207B2
公开(公告)日：2006-10-31
申请号：US10756661
申请日：2004-01-12
IPC分类号： G11C5/02
CPC分类号： G11C13/003 , G11C17/16 , G11C17/18 , G11C2213/76
摘要： A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element. The reference element may comprise a tunnel-junction device and be used with a current source to fuse a memory storage element without fusing a tunnel-junction device of an associated control element. Methods of making the memory structure and using it in electronic devices are disclosed.
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公开(公告)号：US06958946B2
公开(公告)日：2005-10-25
申请号：US10264153
申请日：2002-10-02
摘要： A memory storage device includes a memory cell configurable to have at least a first conductive state and includes a first and second conductor each electrically coupled to the memory cell. A regulation circuit is configured to regulate a sense voltage on the second conductor to be independent of a current conducted through the first conductor when the memory cell is configured to have the first conductive state.
摘要翻译： 存储器存储器件包括可配置为具有至少第一导电状态并且包括电耦合到存储器单元的第一和第二导体的存储单元。 调节电路被配置为当存储单元被配置为具有第一导通状态时，调节第二导体上的感测电压，以独立于通过第一导体传导的电流。
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公开(公告)号：US20050167787A1
公开(公告)日：2005-08-04
申请号：US10772945
申请日：2004-02-04
CPC分类号： H01L27/101
摘要： A memory array has a multiplicity of row conductors and a multiplicity of column conductors, the row conductors and column conductors being arranged to cross at cross-points, and has a memory cell disposed at each cross-point, each memory cell having a storage element and a control element coupled in series between a row conductor and a column conductor, and each control element including a silicon-rich insulator. Methods for fabricating the memory array are disclosed.
摘要翻译： 存储器阵列具有多个行导体和多个列导体，行导体和列导体布置成在交叉点处交叉，并且具有设置在每个交叉点处的存储单元，每个存储单元具有存储元件 以及串联耦合在行导体和列导体之间的控制元件，并且每个控制元件包括富硅绝缘体。 公开了制造存储器阵列的方法。
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公开(公告)号：US06873543B2
公开(公告)日：2005-03-29
申请号：US10448574
申请日：2003-05-30
申请人： Kenneth Kay Smith , Andrew VanBrocklin , Peter Fricke , Frederick A. Perner , Kenneth James Eldredge
发明人： Kenneth Kay Smith , Andrew VanBrocklin , Peter Fricke , Frederick A. Perner , Kenneth James Eldredge
CPC分类号： G11C29/026 , G11C11/16 , G11C29/028 , G11C29/50
摘要： Embodiments of the present invention provide a memory device. In one embodiment, the memory device comprises an array of memory cells configured to provide resistive states, a read circuit configured to sense the resistive states and a resistor. The resistor is configured to provide a resistance to the read circuit that is configured to select the resistor and sense the resistance to test the read circuit.
摘要翻译： 本发明的实施例提供一种存储装置。 在一个实施例中，存储器件包括被配置为提供电阻状态的存储器单元的阵列，被配置为感测电阻状态的读取电路和电阻器。 电阻器被配置为提供对被配置为选择电阻器并且感测电阻以测试读取电路的读取电路的电阻。
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公开(公告)号：US06842369B2
公开(公告)日：2005-01-11
申请号：US10141609
申请日：2002-05-07
摘要： An intermesh memory device includes memory components that each have a determinable resistance value and electronic switches that each control current through one or more of the memory components such that a potential is applied to the memory components. A first electronic switch of the intermesh memory device is electrically coupled to an input of a memory component and a second electronic switch is electrically coupled to an output of the memory component. The first electronic switch and the second electronic switch are configured together to apply a potential to the memory component.
摘要翻译： 互相间存储器件包括每个具有可确定电阻值的存储器组件和每个通过一个或多个存储器组件控制电流的电子开关，使得将电位施加到存储器组件。 互连存储器件的第一电子开关电耦合到存储器组件的输入端，而第二电子开关电耦合到存储器组件的输出端。 第一电子开关和第二电子开关被配置在一起以向存储器组件施加电位。
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公开(公告)号：US06821848B2
公开(公告)日：2004-11-23
申请号：US10286157
申请日：2002-10-30
申请人： Dennis Lazaroff , Kenneth M. Kramer , James E. Ellenson , Neal W. Meyer , David Punsalan , Kurt Ulmer , Peter Fricke , Andrew Koll , Andrew L. Van Brocklin
发明人： Dennis Lazaroff , Kenneth M. Kramer , James E. Ellenson , Neal W. Meyer , David Punsalan , Kurt Ulmer , Peter Fricke , Andrew Koll , Andrew L. Van Brocklin
IPC分类号： H01L21336
CPC分类号： G11C13/003 , G11C17/16 , G11C17/18 , G11C2213/76
摘要： Tunnel-junction structures are fabricated by any of a set of related methods that form two or more tunnel junctions simultaneously. The fabrication methods disclosed are compatible with conventional CMOS fabrication practices, including both single damascene and dual damascene processes. The simultaneously formed tunnel junctions may have different areas. In some embodiments, tub-well structures are formed with sloped sidewalls. In some embodiments, an oxide-metal-oxide film stack on the sidewall of a tub-well is etched to form the tunnel junctions. Memory circuits, other integrated circuit structures, substrates carrying microelectronics, and other electronic devices made by the methods are disclosed.
摘要翻译： 隧道结结构通过同时形成两个或更多个隧道结的一组相关方法中的任一种来制造。 所公开的制造方法与常规CMOS制造实践兼容，包括单镶嵌和双镶嵌工艺。 同时形成的隧道结可以具有不同的区域。 在一些实施例中，浴盆结构形成有倾斜的侧壁。 在一些实施例中，蚀刻在浴缸的侧壁上的氧化物 - 金属氧化物膜堆叠以形成隧道结。 公开了存储电路，其它集成电路结构，携带微电子的衬底以及通过该方法制造的其它电子器件。
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