Curable temperature indicating composition
    1.
    发明授权
    Curable temperature indicating composition 失效
    可固化温度指示组成

    公开(公告)号:US4925727A

    公开(公告)日:1990-05-15

    申请号:US403451

    申请日:1982-07-30

    IPC分类号: B41M5/28 G01K11/16

    摘要: A temperature indicating composition is provided for use on a recoverable article so that heating to produce recovery or to activate a heat-activatable sealant can be monitored. The composition comprises a thermochromic colorant in a binder that can be cured by UV radiation. Such a composition can be applied rapidly to polyolefin substrates by printing.

    摘要翻译: 提供温度指示组合物用于可回收制品,从而可以监测加热以产生回收或活化可热激活的密封剂。 该组合物包含可通过UV辐射固化的粘合剂中的热变色着色剂。 这样的组合物可以通过印刷快速地应用于聚烯烃基材。

    Thermochromic composition
    2.
    发明授权
    Thermochromic composition 失效
    热变色组合物

    公开(公告)号:US4743398A

    公开(公告)日:1988-05-10

    申请号:US855026

    申请日:1986-04-22

    摘要: A temperature indicating composition is provided for use on recoverable articles so that heating to produce recovery or to activate a heat-activatable sealant can be monitored. The composition comprises a thermochromic colorant in a binder and an activator that causes the thermochromic colorant to change color at a temperature lower than the temperature at which the colorant would change temperature in the absence of the activator. The thermochromic colorant can be folic acid and the activator can be an acid that has a pK of less than 4.2.

    摘要翻译: 提供温度指示组合物用于可回收制品,从而可以监测加热以产生回收或活化可热激活的密封剂。 该组合物包含粘合剂中的热变色着色剂和活化剂,其使热变色着色剂在低于着色剂在不存在活化剂的情况下改变温度的温度的温度下变色。 热变色着色剂可以是叶酸,活化剂可以是pK小于4.2的酸。

    Bi-layer resist process for semiconductor processing
    3.
    发明授权
    Bi-layer resist process for semiconductor processing 失效
    用于半导体处理的双层抗蚀剂工艺

    公开(公告)号:US5286607A

    公开(公告)日:1994-02-15

    申请号:US803541

    申请日:1991-12-09

    申请人: Andrew V. Brown

    发明人: Andrew V. Brown

    IPC分类号: G03F7/09 G03C5/00 G03F7/36

    CPC分类号: G03F7/094 Y10S438/95

    摘要: A multi-level patterning process for use in the semiconductor fabrication technology that will consistently produce a very fine and well defined pattern, and which can be re-worked, especially at the early stages of the process is accomplished. In the process, a thick resist, such as a Novolak resin with suitable additives is spun on a wafer. This material is heavily dyed to the exposing wave length of the radiant energy source of the stepper. The planerizing layer is exposed to a silicon containing atmosphere, such as hexamethyldisilazane (HMDS) for a period of time and a temperature sufficient for the silicon to penetrate a short distance, for example about 0.25 micrometers into the resist. The resist is crosslinked during this bake or during a subsequent bake. These wafers are now ready for standard resist processing. The resist is spun, exposed, and developed. The wafers are then inspected for error. Rework can be accomplished at the stage by stripping the top resist and recoating. After inspection, the wafers go through a short RIE that transfers the pattern down through the silicon containing layer. This etch is then converted to an oxygen gas only etch that etches the rest of the way through the planerizing layer. The silicon containing resist layer acts as an etch mask. The wafer has now completed the lithography step and is ready for further processing.

    摘要翻译: 用于半导体制造技术的多级图案化工艺将一致地产生非常精细和明确定义的图案,并且可以重新工作,特别是在该工艺的早期阶段。 在该方法中,将厚抗蚀剂,例如具有合适添加剂的酚醛清漆树脂在晶片上纺丝。 该材料被严重染色到步进器的辐射能源的曝光波长。 将平整层暴露于含硅气氛(例如六甲基二硅氮烷(HMDS))一段时间,并使硅足以使硅穿透抗蚀剂的较短距离,例如约0.25微米。 在烘烤期间或在随后的烘烤期间,抗蚀剂交联。 这些晶圆现在可以用于标准抗蚀剂处理。 抗蚀剂被旋转,曝光和显影。 然后检查晶圆是否有错误。 通过剥离顶层抗蚀剂和重涂,可以在舞台上完成返工。 在检查之后,晶片经过将图案向下传送通过含硅层的短RIE。 然后将该蚀刻转变成仅氧化气蚀刻,其蚀刻其余部分通过平整层。 含硅抗蚀剂层用作蚀刻掩模。 晶圆已经完成光刻步骤,并准备好进一步处理。

    Polymerizable planarization layer for integrated circuit structures
    4.
    发明授权
    Polymerizable planarization layer for integrated circuit structures 失效
    用于集成电路结构的可聚合平面化层

    公开(公告)号:US4619837A

    公开(公告)日:1986-10-28

    申请号:US697363

    申请日:1985-02-01

    申请人: Andrew V. Brown

    发明人: Andrew V. Brown

    摘要: The invention comprises an improvement in the process of manufacturing an integrated circuit structure having stepped topography which comprises coating the integrated circuit structure with a polymerizable material in the substantial absence of a solvent and then polymerizing the material to provide a substantially planar surface on the integrated circuit structure.

    摘要翻译: 本发明包括制造具有阶梯形状的集成电路结构的过程的改进,其包括在基本上不存在溶剂的情况下用可聚合材料涂覆集成电路结构,然后聚合材料以在集成电路上提供基本平坦的表面 结构体。