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1.发明申请Process and apparatus for placement of cells in an IC during floorplan creation 有权在建立平面布置图时，将单元格放置在IC中的过程和装置公开(公告)号：US20050091625A1
公开(公告)日：2005-04-28
申请号：US10694208
申请日：2003-10-27
CPC分类号： G06F17/5072
摘要： Objects are placed in a rectangle and their coordinates of the objects and are adjusted to establish a substantially uniform density of objects in the rectangle. The evaluation of coordinates is performed by placing the wires between cells coordinates and adjusting the cell coordinates to connect the cells to the wires. The substantially uniform density is achieved by dividing the rectangle into first and second rectangles having equal free areas and into third and fourth rectangles having equal areas of objects. The coordinates of the objects are adjusted based on boundaries between the first and second rectangles and between the third and fourth rectangles.
摘要翻译： 将对象放置在矩形中，并且对象的坐标进行调整，以在矩形中建立大致均匀的对象密度。 坐标的评估是通过将电线放在单元之间进行坐标并调整单元坐标来连接单元与导线。 通过将矩形分成具有相等空闲区域的第一和第二矩形以及具有相同面积的物体的第三和第四矩形来实现基本上均匀的密度。 基于第一和第二矩形之间以及第三和第四矩形之间的边界来调整对象的坐标。
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公开(公告)号：US20070230621A1
公开(公告)日：2007-10-04
申请号：US11758975
申请日：2007-06-06
IPC分类号： H03K9/00
CPC分类号： G06F17/18
摘要： A Gaussian noise is simulated by discrete analogue ri,j. A first parameter α and pluralities of first and second integers i and j are selected. A plurality of points i,j are identified and a magnitude si,j is calculated for each point based on α, i and j. The discrete analogue ri,j is based on a respective si,j. Examples are given of α = 2 B - A 2 B and D>i≧0 and 2C>j≧0, where B≧0, 2B>A>0, C≧1 and D≧1, and magnitude s i , j = 1 - α i + α i · 1 - α 2 C · j or s D - 1 , j = 1 - α D - 1 + α D - 1 · 1 2 C · j . In some embodiments, a segment is defined based on α and i. The segment is divided into points based on respective values of j, and the magnitude is calculated for each point of the segment. The defining and dividing segments and calculating the magnitude is iteratively repeated for each value of i.
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公开(公告)号：US20050240889A1
公开(公告)日：2005-10-27
申请号：US10830542
申请日：2004-04-23
CPC分类号： G06F17/5072
摘要： Cells are placed into an integrated circuit floorplan by creating clusters of cells in modules, each cluster being composed of cells in a path connected to at least one flip-flop in the module, or of cells that are not in a path connected to any flip-flop. Regions are defined in the floorplan for placement of modules, and the clusters are placed into optimal locations in modules and placing the modules into optimal locations in the regions. T coordinates for the wires, modules and clusters are selectively recalculated. The clusters are moved in the floorplan for more uniform density, and the modules are assigned to regions based on module coordinates.
摘要翻译： 通过在模块中创建单元格群，将单元放置在集成电路平面布置图中，每个簇由连接到模块中的至少一个触发器的路径中的单元或者不连接到任何翻转的路径的单元组成 -flop。 区域在布局图中定义，用于放置模块，并将集群放置在模块中的最佳位置，并将模块放置在区域中的最佳位置。 有选择地重新计算电线，模块和集群的T坐标。 群集在平面图中移动以获得更均匀的密度，并且将模块分配给基于模块坐标的区域。
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公开(公告)号：US20060107247A1
公开(公告)日：2006-05-18
申请号：US10990589
申请日：2004-11-17
CPC分类号： G06F17/5072
摘要： A memory generation and placement flow system that receives a customer memory design and places the customer memory design within a customizable standardized integrated circuit design. The memory generation and placement flow system includes a memory librarian tool, a memory estimator tool, and a memory placer tool.
摘要翻译： 存储器生成和放置流程系统，其接收客户存储器设计，并将客户存储器设计放置在可定制的标准化集成电路设计中。 存储器生成和放置流程系统包括存储库管理器工具，存储器估计器工具和存储器存储器工具。
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5.发明申请公开(公告)号：US20070136704A1
公开(公告)日：2007-06-14
申请号：US11298894
申请日：2005-12-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译： 提供了一种用于创建和使用存储器定时数据库的方法和装置。 定义了多个表征存储器，其可被映射到存储器资源。 每个表征存储器具有不同的存储器参数。 还定义了将每个表征存储器平铺到存储器资源的多种变型。 每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。
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公开(公告)号：US07155688B2
公开(公告)日：2006-12-26
申请号：US10990589
申请日：2004-11-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A memory generation and placement flow system that receives a customer memory design and places the customer memory design within a customizable standardized integrated circuit design. The memory generation and placement flow system includes a memory librarian tool, a memory estimator tool, and a memory placer tool.
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7.发明申请Method and system for converting netlist of integrated circuit between libraries 失效图书馆集成电路网表的转换方法及系统公开(公告)号：US20070094621A1
公开(公告)日：2007-04-26
申请号：US11257206
申请日：2005-10-24
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The present invention provides a method for converting a netlist of an integrated circuit from a first library to a second library. The first library may include logic cells AND, OR and NOT, and the second library may include logic cells NAND and NOR. The method includes steps as follows. Logic cells of the netlist are topologically sorted from outputs to inputs. AND and OR cells of the netlist are replaced with NOT, NAND and NOR cells. Simplification of the netlist is performed in a topological order.
摘要翻译： 本发明提供一种用于将集成电路的网表从第一库转换为第二库的方法。 第一个库可以包括逻辑单元AND，OR和NOT，并且第二库可以包括逻辑单元NAND和NOR。 该方法包括以下步骤。 网表的逻辑单元从输出到输入进行拓扑分类。 将网表的AND和OR单元替换为NOT，NAND和NOR单元。 网表的简化是以拓扑顺序执行的。
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8.发明申请Method and system for outputting a sequence of commands and data described by a flowchart 有权用于输出由流程图描述的命令和数据序列的方法和系统公开(公告)号：US20070169009A1
公开(公告)日：2007-07-19
申请号：US11260517
申请日：2005-10-27
IPC分类号： G06F9/45
CPC分类号： G06F8/66
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译： 本发明是用于输出由流程图描述的命令和数据序列的方法和系统。 该方法包括以下步骤。 接收描述命令和数据序列的流程图。 流程图包括多个流程图符号。 多个流程图符号中的每一个被分配有ROM（只读存储器）记录。 分配的ROM记录存储在ROM中。 产生处理器以包括ROM，其中处理器接收CLOCK信号，RESET信号，ENABLE信号和N个二进制输入x 1，x 2， 。 。 。 并且输出命令和数据的序列。
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公开(公告)号：US20070094633A1
公开(公告)日：2007-04-26
申请号：US11257289
申请日：2005-10-24
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/64
摘要： The present invention provides a method for mapping a netlist of an integrated circuit to a design. The method includes steps as follows. Chaos algorithm is used to obtain most favorable places in the design for cells from the netlist. Kuhn's algorithm is utilized to assign each cell of the netlist a cell in a template so that, for each cell of the netlist, its place in the template is as close as possible to its place obtained by the chaos algorithm. Simulating annealing optimization technique is applied to reduce a sum of wire length of the design.
摘要翻译： 本发明提供了一种用于将集成电路的网表映射到设计的方法。 该方法包括以下步骤。 混沌算法用于从网表中为单元格设计获得最有利的位置。 Kuhn算法用于将网表中的每个单元格分配给模板中的单元，使得对于网表的每个单元，其在模板中的位置尽可能靠近其通过混沌算法获得的位置。 应用模拟退火优化技术减少设计线长度的总和。
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公开(公告)号：US07193905B1
公开(公告)日：2007-03-20
申请号：US11259228
申请日：2005-10-25
CPC分类号： G11C11/418 , G11C8/10
摘要： An RRAM flip-flop rcell memory of the type having a write address decoder, a read address decoder, a set of n flip flops, one AND gate associated with each flip flop in the set, a set of w OR gates where each of the w OR gates in the set has n inputs, the improvement comprising only one write address decoder, and replacing the read address decoder and the set of AND gates and the set of OR gates with no more than one multiplexor, thereby providing a reduction in a path length from an rcell memory input to an rcell memory output and thereby improving timing of the rcell memory, while reducing fanout size of the rcell. In a preferred embodiment, the multiplexor includes fewer than w OR gates, and fewer than n AND gates, and two decoders, which are commonly connected to outputs of the n flip flops.
摘要翻译： 具有写地址解码器，读地址解码器，一组n个触发器，与该组中的每个触发器相关联的一个与门的RRAM触发器rcell存储器，一组w OR门，其中每个 该组中的w或门具有n个输入，改进仅包括一个写地址解码器，并且用不多于一个多路复用器替换读地址解码器和与门组和OR门组，从而提供 从rcell存储器输入到rcell存储器输出的路径长度，从而提高rcell存储器的定时，同时减少rcell的扇出大小。 在优选实施例中，多路复用器包括通常连接到n个触发器的输出的少于或几个门，以及少于n个与门和两个解码器。
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