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1.发明申请Method and system for converting netlist of integrated circuit between libraries 失效图书馆集成电路网表的转换方法及系统公开(公告)号：US20070094621A1
公开(公告)日：2007-04-26
申请号：US11257206
申请日：2005-10-24
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The present invention provides a method for converting a netlist of an integrated circuit from a first library to a second library. The first library may include logic cells AND, OR and NOT, and the second library may include logic cells NAND and NOR. The method includes steps as follows. Logic cells of the netlist are topologically sorted from outputs to inputs. AND and OR cells of the netlist are replaced with NOT, NAND and NOR cells. Simplification of the netlist is performed in a topological order.
摘要翻译： 本发明提供一种用于将集成电路的网表从第一库转换为第二库的方法。 第一个库可以包括逻辑单元AND，OR和NOT，并且第二库可以包括逻辑单元NAND和NOR。 该方法包括以下步骤。 网表的逻辑单元从输出到输入进行拓扑分类。 将网表的AND和OR单元替换为NOT，NAND和NOR单元。 网表的简化是以拓扑顺序执行的。
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公开(公告)号：US20070094633A1
公开(公告)日：2007-04-26
申请号：US11257289
申请日：2005-10-24
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/64
摘要： The present invention provides a method for mapping a netlist of an integrated circuit to a design. The method includes steps as follows. Chaos algorithm is used to obtain most favorable places in the design for cells from the netlist. Kuhn's algorithm is utilized to assign each cell of the netlist a cell in a template so that, for each cell of the netlist, its place in the template is as close as possible to its place obtained by the chaos algorithm. Simulating annealing optimization technique is applied to reduce a sum of wire length of the design.
摘要翻译： 本发明提供了一种用于将集成电路的网表映射到设计的方法。 该方法包括以下步骤。 混沌算法用于从网表中为单元格设计获得最有利的位置。 Kuhn算法用于将网表中的每个单元格分配给模板中的单元，使得对于网表的每个单元，其在模板中的位置尽可能靠近其通过混沌算法获得的位置。 应用模拟退火优化技术减少设计线长度的总和。
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3.发明申请Process and apparatus for placement of cells in an IC during floorplan creation 有权在建立平面布置图时，将单元格放置在IC中的过程和装置公开(公告)号：US20050091625A1
公开(公告)日：2005-04-28
申请号：US10694208
申请日：2003-10-27
CPC分类号： G06F17/5072
摘要： Objects are placed in a rectangle and their coordinates of the objects and are adjusted to establish a substantially uniform density of objects in the rectangle. The evaluation of coordinates is performed by placing the wires between cells coordinates and adjusting the cell coordinates to connect the cells to the wires. The substantially uniform density is achieved by dividing the rectangle into first and second rectangles having equal free areas and into third and fourth rectangles having equal areas of objects. The coordinates of the objects are adjusted based on boundaries between the first and second rectangles and between the third and fourth rectangles.
摘要翻译： 将对象放置在矩形中，并且对象的坐标进行调整，以在矩形中建立大致均匀的对象密度。 坐标的评估是通过将电线放在单元之间进行坐标并调整单元坐标来连接单元与导线。 通过将矩形分成具有相等空闲区域的第一和第二矩形以及具有相同面积的物体的第三和第四矩形来实现基本上均匀的密度。 基于第一和第二矩形之间以及第三和第四矩形之间的边界来调整对象的坐标。
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4.发明申请Method and system for outputting a sequence of commands and data described by a flowchart 有权用于输出由流程图描述的命令和数据序列的方法和系统公开(公告)号：US20070169009A1
公开(公告)日：2007-07-19
申请号：US11260517
申请日：2005-10-27
IPC分类号： G06F9/45
CPC分类号： G06F8/66
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译： 本发明是用于输出由流程图描述的命令和数据序列的方法和系统。 该方法包括以下步骤。 接收描述命令和数据序列的流程图。 流程图包括多个流程图符号。 多个流程图符号中的每一个被分配有ROM（只读存储器）记录。 分配的ROM记录存储在ROM中。 产生处理器以包括ROM，其中处理器接收CLOCK信号，RESET信号，ENABLE信号和N个二进制输入x 1，x 2， 。 。 。 并且输出命令和数据的序列。
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公开(公告)号：US07193905B1
公开(公告)日：2007-03-20
申请号：US11259228
申请日：2005-10-25
CPC分类号： G11C11/418 , G11C8/10
摘要： An RRAM flip-flop rcell memory of the type having a write address decoder, a read address decoder, a set of n flip flops, one AND gate associated with each flip flop in the set, a set of w OR gates where each of the w OR gates in the set has n inputs, the improvement comprising only one write address decoder, and replacing the read address decoder and the set of AND gates and the set of OR gates with no more than one multiplexor, thereby providing a reduction in a path length from an rcell memory input to an rcell memory output and thereby improving timing of the rcell memory, while reducing fanout size of the rcell. In a preferred embodiment, the multiplexor includes fewer than w OR gates, and fewer than n AND gates, and two decoders, which are commonly connected to outputs of the n flip flops.
摘要翻译： 具有写地址解码器，读地址解码器，一组n个触发器，与该组中的每个触发器相关联的一个与门的RRAM触发器rcell存储器，一组w OR门，其中每个 该组中的w或门具有n个输入，改进仅包括一个写地址解码器，并且用不多于一个多路复用器替换读地址解码器和与门组和OR门组，从而提供 从rcell存储器输入到rcell存储器输出的路径长度，从而提高rcell存储器的定时，同时减少rcell的扇出大小。 在优选实施例中，多路复用器包括通常连接到n个触发器的输出的少于或几个门，以及少于n个与门和两个解码器。
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公开(公告)号：US20050086624A1
公开(公告)日：2005-04-21
申请号：US10688460
申请日：2003-10-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Objects are assigned to points in a rectangle by dividing the rectangle is divided into a plurality of smaller rectangles and applying an object assignment procedure, such as Kuhn's algorithm, to initially assigned objects in each second rectangle. The initial assignment is performed by calculating a maximal cost of assignment of objects to points, and selecting an assignment of objects having a minimum value of maximal cost, identified by iteratively recalculating the maximal matching assignment based on a midpoint of between the minimum and maximum costs.
摘要翻译： 通过将矩形划分为多个较小的矩形并将对象分配过程（例如Kuhn算法）应用于每个第二矩形中的初始分配对象，将对象分配给矩形中的点。 通过计算对象到点的分配的最大成本并且选择具有最大成本的最小值的对象的分配来执行初始分配，通过基于最小和最大成本之间的中点迭代地重新计算最大匹配分配来识别 。
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7.发明授权Multimode delay analysis for simplifying integrated circuit design timing models 失效用于简化集成电路设计时序模型的多模延迟分析公开(公告)号：US07512918B2
公开(公告)日：2009-03-31
申请号：US11205365
申请日：2005-08-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of analyzing multimode delay in an integrated circuit design to produce a timing model for the integrated circuit design, by inputting a net list, IO arc delays, interconnection arc delays, and constant nets with assigned Boolean functions for the integrated circuit design, propagating the constant nets and assigning Boolean conditions to the IO arc delays and the interconnection arc delays, evaluating timing path delays and conditions for the integrated circuit design, creating the integrated circuit design timing model parameters, and outputting the integrated circuit design timing model. The method is especially desirable for netlists with very complicated mixing logics that include muxing of clocks. In particular, RRAMs are such netlists.
摘要翻译： 一种分析集成电路设计中的多模延迟的方法，通过输入集成电路设计的网络列表，IO弧延迟，互连电弧延迟和具有分配布尔函数的恒定网络来生成集成电路设计的定时模型，传播 恒定网络和布尔条件给IO弧延迟和互连电弧延迟，评估集成电路设计的定时路径延迟和条件，创建集成电路设计时序模型参数，并输出集成电路设计时序模型。 该方法对于具有非常复杂的混合逻辑（包括时钟复用）的网表来说是特别需要的。 特别地，RRAM是这样的网表。
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公开(公告)号：US20060117281A1
公开(公告)日：2006-06-01
申请号：US10999468
申请日：2004-11-30
CPC分类号： G06F17/5022
摘要： The present invention provides a method of verification of a RRAM tiling netlist. The method may include steps as follows. Properties “memory_number”, “clock_number” and “netlist_part” of all nets and cells of a RRAM tiling netlist are set to a value 0. A boolean function 0 is assigned to all ground nets of the RRAM tiling netlist, and a boolean function 1 is assigned to all power nets of the RRAM tiling netlist. The RRAM tiling netlist is verified for each customer memory Memk, k=1, 2, . . . , N.
摘要翻译： 本发明提供了一种RRAM拼接网表的验证方法。 该方法可以包括以下步骤。 属性RRAM平铺网表的所有网络和单元的“memory_number”，“clock_number”和“netlist_part”被设置为值0。 布尔函数0被分配给RRAM平铺网表的所有接地网，并且布尔函数1被分配给RRAM平铺网表的所有电网。 对于每个客户存储器验证RRAM平铺网表，其中k = 1,2，...。 。 。 ，N.
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9.发明申请Method and system for outputting a sequence of commands and data described by a flowchart 失效用于输出由流程图描述的命令和数据序列的方法和系统公开(公告)号：US20060020927A1
公开(公告)日：2006-01-26
申请号：US10894781
申请日：2004-07-20
IPC分类号： G06F9/45
CPC分类号： G06F17/5054
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. In an exemplary aspect of the present invention, a method for outputting a sequence of commands and data described by a flowchart includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A module (e.g., a CKD, or the like) is generated to include the ROM, wherein the module receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译： 本发明是用于输出由流程图描述的命令和数据序列的方法和系统。 在本发明的一个示例性方面，用于输出由流程图描述的命令和数据序列的方法包括以下步骤。 接收描述命令和数据序列的流程图。 流程图包括多个流程图符号。 多个流程图符号中的每一个被分配有ROM（只读存储器）记录。 分配的ROM记录存储在ROM中。 生成模块（例如，CKD等）以包括ROM，其中模块接收CLOCK信号，RESET信号，ENABLE信号和N个二进制输入x 1， x 2，...， 。 。 并且输出命令和数据的序列。
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公开(公告)号：US20060010092A1
公开(公告)日：2006-01-12
申请号：US10875128
申请日：2004-06-23
CPC分类号： G06F17/5045 , G06F12/0292 , G06Q10/0875 , G06Q99/00
摘要： A user-defined memory design is mapped to memories of a base platform for an IC that contains a plurality of memory sets, each containing a plurality of memories of a predetermined type. An optimal memory set is selected from the plurality of memory sets for the design by selecting a preference rate for each memory set from the plurality of sets based on the design and its connections to portions of the IC, and selectively assigning the design to one of the memory sets based on the preference rate. The design is optimally mapped to a plurality of memories of the selected memory set by defining an index of the position of each customer memory in the selected memory set. The customer memories in the selected memory set are arranged in an order, and successive numbers of memories of the selected memory set are assigned to each customer memory in order.
摘要翻译： 用户定义的存储器设计被映射到用于IC的基础平台的存储器，该存储器包含多个存储器组，每个存储器组包含预定类型的多个存储器。 从设计的多个存储器集合中选择最佳存储器集合，其基于设计及其与IC的部分的连接，从多个集合中选择每个存储器组的偏好率，并且将该设计选择性地分配给 基于优先级的内存集。 通过定义所选择的存储器组中的每个顾客存储器的位置的索引，将设计最佳地映射到所选存储器组的多个存储器。 所选择的存储器组中的客户存储器按顺序排列，并且所选择的存储器组的连续数量的存储器按顺序分配给每个客户存储器。
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