公开(公告)号：US07557608B2

公开(公告)日：2009-07-07

申请号：US11498214

申请日：2006-08-01

申请人： Andy L Lee ,  Wanli Chang ,  Cameron McClintock ,  John E Turner ,  Brian D Johnson ,  Chiao Kai Hwang ,  Richard Yen-Hsiang Chang ,  Richard G Cliff

发明人： Andy L Lee ,  Wanli Chang ,  Cameron McClintock ,  John E Turner ,  Brian D Johnson ,  Chiao Kai Hwang ,  Richard Yen-Hsiang Chang ,  Richard G Cliff

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K17/063 ,  H03K19/177 ,  H03K19/1778

摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

摘要翻译： 提出了用于低压系统的增强型门控结构，其中Vt对单晶闸管通道通过的信号范围的影响减小。 在一种布置中，通过应用较高的VGATE来提高通过NMOS通道传播的信号的VGATE-Vt极限; 在另一种布置中，Vt被降低。 传统上使用单通道闸门的CMOS传动闸门的使用也被提出。

公开(公告)号：US07119574B1

公开(公告)日：2006-10-10

申请号：US10637258

申请日：2003-08-08

申请人： Andy L Lee ,  Wanli Chang ,  Cameron McClintock ,  John E Turner ,  Brian D Johnson ,  Chiao Kai Hwang ,  Richard Y Chang ,  Richard G Cliff

发明人： Andy L Lee ,  Wanli Chang ,  Cameron McClintock ,  John E Turner ,  Brian D Johnson ,  Chiao Kai Hwang ,  Richard Y Chang ,  Richard G Cliff

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K17/063 ,  H03K19/177 ,  H03K19/1778

摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE−Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

摘要翻译： 提出了用于低电压系统的增强型门控结构，其中V 对由单晶闸管通过的信号范围的影响减小。 在一种布置中，通过施加更高的V门极来提高通过NMOS通孔传播的信号的V门极限极限。 在另一种布置中，V 降低。 传统上使用单通道闸门的CMOS传动闸门的使用也被提出。

公开(公告)号：US07319253B2

公开(公告)日：2008-01-15

申请号：US10883091

申请日：2004-07-01

申请人： Lakhbeer S Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John E Turner

发明人： Lakhbeer S Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John E Turner

IPC分类号： H01L27/108

CPC分类号： G11C11/412 ,  H01L27/0207 ,  H01L27/11807

摘要： A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

摘要翻译： 用于现场可编程门阵列（“FPGA”）集成电路（“IC”）器件的配置存储单元（“CRAM”）被赋予增加的对单一事件不正常（“SEU”）的阻力。 CRAM的输入节点的栅极结构的一部分相对于栅极结构的其余部分的标称尺寸增大。 放大栅极结构的一部分位于与IC的N阱区电容性相邻的位置，另一部分位于与IC的P阱区电容相邻的位置。 这种布置使得输入节点增加了抵抗SEU的电容，而与输入节点的逻辑电平无关。 本发明也可应用于任何类型的存储器单元的任何节点，其对期望增加的对SEU的抗性。