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    Differential interconnection circuits in programmable logic devices
    6.
    发明授权
    Differential interconnection circuits in programmable logic devices 有权
    可编程逻辑器件中的差分互连电路

    公开(公告)号：US06842040B1

    公开(公告)日：2005-01-11

    申请号：US10319329

    申请日：2002-12-13

    申请人： Wanli Chang ,  Andy Lee ,  Cameron McClintock ,  Richard Cliff ,  Richard Yen-Hsiang Chang

    发明人： Wanli Chang ,  Andy Lee ,  Cameron McClintock ,  Richard Cliff ,  Richard Yen-Hsiang Chang

    IPC分类号： H03K5/151 ,  H03K19/017 ,  H03K19/177

    CPC分类号： H03K19/17736 ,  H03K5/151 ,  H03K19/01721 ,  H03K19/17784

    摘要： At least some of the interconnection signaling on a programmable logic device (“PLD”) is by differential signaling using differential driver circuitry to apply differential signals to a pair of conductors that extend to differential receiver circuitry. Such differential interconnection signaling helps the PLD operate satisfactorily with lower power supply voltages. The conductors in each differential signaling pair may cross over one another at various intervals in order to help reduce the adverse effects of capacitive coupling between adjacent and parallel signaling paths.

    摘要翻译： 可编程逻辑器件（“PLD”）上的至少一些互连信号通过使用差分驱动器电路的差分信号来将差分信号施加到延伸到差分接收器电路的一对导体。 这种差分互连信令有助于PLD在较低的电源电压下令人满意地工作。 每个差分信号对中的导体可以以不同的间隔彼此交叉，以便有助于减少相邻和并行信令路径之间的电容耦合的不利影响。

    Differential interconnection circuits in programmable logic devices
    7.
    发明授权
    Differential interconnection circuits in programmable logic devices 有权
    可编程逻辑器件中的差分互连电路

    公开(公告)号：US06515508B1

    公开(公告)日：2003-02-04

    申请号：US09853439

    申请日：2001-05-10

    申请人： Wanli Chang ,  Andy Lee ,  Cameron McClintock ,  Richard Cliff ,  Richard Yen-Hsiang Chang

    发明人： Wanli Chang ,  Andy Lee ,  Cameron McClintock ,  Richard Cliff ,  Richard Yen-Hsiang Chang

    IPC分类号： H03K19177

    CPC分类号： H03K19/17736 ,  H03K5/151 ,  H03K19/01721 ,  H03K19/17784

    摘要： At least some of the interconnection signaling on a programmable logic device (“PLD”) is by differential signaling using differential driver circuitry to apply differential signals to a pair of conductors that extend to differential receiver circuitry. Such differential interconnection signaling helps the PLD operate satisfactorily with lower power supply voltages. The conductors in each differential signaling pair may cross over one another at various intervals in order to help reduce the adverse effects of capacitive coupling between adjacent and parallel signaling paths.

    摘要翻译： 可编程逻辑器件（“PLD”）上的至少一些互连信号通过使用差分驱动器电路的差分信号来将差分信号施加到延伸到差分接收器电路的一对导体。 这种差分互连信令有助于PLD在较低的电源电压下令人满意地工作。 每个差分信号对中的导体可以以不同的间隔彼此交叉，以便有助于减少相邻和并行信令路径之间的电容耦合的不利影响。

    Programmable logic array integrated circuits
    8.
    发明授权
    Programmable logic array integrated circuits 失效
    可编程逻辑阵列集成电路

    公开(公告)号：US5828229A

    公开(公告)日：1998-10-27

    申请号：US847004

    申请日：1997-05-01

    申请人： Richard G. Cliff ,  L. Todd Cope ,  Cameron McClintock ,  William Leong ,  James Allen Watson ,  Joseph Huang ,  Bahram Ahanin ,  Chiakang Sung ,  Wanli Chang

    发明人： Richard G. Cliff ,  L. Todd Cope ,  Cameron McClintock ,  William Leong ,  James Allen Watson ,  Joseph Huang ,  Bahram Ahanin ,  Chiakang Sung ,  Wanli Chang

    IPC分类号： G01R31/3185 ,  G11C8/12 ,  G11C8/16 ,  G11C29/32 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1737 ,  G11C29/32 ,  G11C8/12 ,  G11C8/16 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1776 ,  H03K19/17764 ,  G01R31/318516

    摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors. A relatively large block of random access memory ("RAM") may be provided on the device for use as read-only memory ("ROM") or RAM during operation of the device to perform logic. The RAM block is connected in the circuitry of the device so that it can be programmed and verified compatibly with other memory on the device. Thereafter the circuitry of the RAM block allows it to be switched over to operation as RAM or ROM during logic operation of the device.

    摘要翻译： 可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。 提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。 此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的 网络。 提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。 多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。 随机存取存储器（“RAM”）相对较大的块可以在设备的操作期间被提供在设备上用作只读存储器（“ROM”）或RAM，以执行逻辑。 RAM块连接在设备的电路中，使其可以与设备上的其他存储器进行编程和验证。 此后，RAM块的电路允许在设备的逻辑运行期间将其切换到作为RAM或ROM的操作。