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    Method and circuit for detecting a fault in a clock signal for microprocessor electronic devices including memory elements
    2.
    再颁专利
    Method and circuit for detecting a fault in a clock signal for microprocessor electronic devices including memory elements 有权
    用于检测包括存储器元件的微处理器电子设备的时钟信号中的故障的方法和电路

    公开(公告)号：USRE38154E1

    公开(公告)日：2003-06-24

    申请号：US09258088

    申请日：1999-02-25

    申请人： Angelo Moroni ,  Flavio Scarra ,  Alberto Taddeo

    发明人： Angelo Moroni ,  Flavio Scarra ,  Alberto Taddeo

    IPC分类号： G11C800

    CPC分类号： G06F11/0757 ,  G06F1/04 ,  G06F1/24 ,  G06F11/073 ,  G06F11/0754 ,  G06F11/0793 ,  G06F11/0796 ,  H03K5/19

    摘要： An electronic device including a microprocessor, a circuit generating a clock signal, and memories of both the volatile type and the non-volatile type, incorporates a circuit for generation of a reset signal capable of detecting a stop in the oscillation of said clock signal and generating a logic signal coupled with the reset input of the microprocessor. The circuit monitors the clock signal applied to the device and, if an irregularity is detected, generate a reset signal holding the microprocessor in a safe state. The reset signal is held until the circuit generating the clock signal resumes normal operation.

    摘要翻译： 包括微处理器，产生时钟信号的电路和易失性类型和非易失性类型的存储器的电子设备包括用于产生能够检测所述时钟信号的振荡中的停止的复位信号的电路，以及 产生与微处理器的复位输入耦合的逻辑信号。 该电路监视施加到设备的时钟信号，如果检测到不规则，则产生将微处理器保持在安全状态的复位信号。 复位信号保持，直到产生时钟信号的电路恢复正常运行。

    Digital correction for missing codes caused by capacitive mismatchings in successive approximation analog-to-digital converters
    4.
    发明授权
    Digital correction for missing codes caused by capacitive mismatchings in successive approximation analog-to-digital converters 失效
    在逐次逼近模数转换器中由电容失配引起的丢失码的数字校正

    公开(公告)号：US5579005A

    公开(公告)日：1996-11-26

    申请号：US356075

    申请日：1994-12-14

    申请人： Angelo Moroni

    发明人： Angelo Moroni

    IPC分类号： H03M1/38 ,  H03M1/06

    CPC分类号： H03M1/0612 ,  H03M1/38

    摘要： An analog-to-digital converter (ADC), comprising an internal digital-to-analog converter (DAC), driven by a successive approximation register (SAR), and a comparator, is provided with a correction logic circuit that controls the execution of a verifying and correcting routine at the end of each conversion routine. Master-Slave cells that compose the SAR are provided with a dedicated circuitry, responding to said correction control circuit, for confirming, incrementing or decrementing the bit stored in the cell by at least an LSB. An extremely simple routine, performed at the end of each conversion cycle, allows correction of incorrectly converted digital data because of the occurrence of missing codes in the internal DAC. The corrector does not require the use of memories and/or analog circuits and is very cost- effective and permits a greatly improved production yield of complex devices containing ADCs.

    摘要翻译： 包括由逐次逼近寄存器（SAR）驱动的内部数模转换器（DAC）和比较器的模数转换器（ADC）设置有校正逻辑电路，其控制执行 每个转换程序结束时的验证和校正程序。 构成SAR的主从单元被提供有专用电路，响应于所述校正控制电路，用于确认，增加或减少存储在单元中的位至少LSB。 在每个转换周期结束时执行的非常简单的例程允许校正由于内部DAC中缺少代码的错误转换的数字数据。 校正器不需要使用存储器和/或模拟电路，并且非常成本有效，并且允许大大提高包含ADC的复杂器件的产量。