公开(公告)号：US07361950B2

公开(公告)日：2008-04-22

申请号：US11162471

申请日：2005-09-12

申请人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  Keith Edward Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert Mark Rassel ,  Anthony Kendall Stamper ,  Kunal Vaed

发明人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  Keith Edward Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert Mark Rassel ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L28/40

摘要： A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by sidewall spacers.

摘要翻译： 在具有顶表面并且包括形成在从浅沟槽隔离（STI）区域中选择的表面中的区域和具有与半导体衬底共面的外表面的掺杂阱的半导体衬底上形成MIM电容器。 电容器底板是形成在半导体衬底中的STI区域上的下电极或由可能具有硅化物表面的在半导体衬底的顶表面中形成的掺杂阱形成的下电极。 电容器HiK电介质层形成在下板上或上。 在电容器下板上方的HiK电介质层上形成电容器第二板。 可以在第二板的上方形成具有顶板的双电容器结构，其中通过侧壁间隔件连接到被第二板保护的下板的通孔。

公开(公告)号：US07915134B2

公开(公告)日：2011-03-29

申请号：US11970555

申请日：2008-01-08

申请人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  Keith Edward Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert Mark Rassel ,  Anthony Kendall Stamper ,  Kunal Vaed

发明人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  Keith Edward Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert Mark Rassel ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC分类号： H01L21/20

CPC分类号： H01L28/40

摘要： A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by side wall spacers.

摘要翻译： 在具有顶表面并且包括形成在从浅沟槽隔离（STI）区域中选择的表面中的区域和具有与半导体衬底共面的外表面的掺杂阱的半导体衬底上形成MIM电容器。 电容器底板是形成在半导体衬底中的STI区域上的下电极或由可能具有硅化物表面的在半导体衬底的顶表面中形成的掺杂阱形成的下电极。 电容器HiK电介质层形成在下板上或上。 在电容器下板上方的HiK电介质层上形成电容器第二板。 可以在第二板的上方形成具有顶板的双电容器结构，其中通过侧壁间隔件连接到被第二板保护的下板的通孔。

公开(公告)号：US20090004809A1

公开(公告)日：2009-01-01

申请号：US11970555

申请日：2008-01-08

申请人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  Keith Edward Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert Mark Rassel ,  Anthony Kendall Stamper ,  Kunal Vaed

发明人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  Keith Edward Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert Mark Rassel ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC分类号： H01L21/20

CPC分类号： H01L28/40

摘要： A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by side wall spacers.

摘要翻译： 在具有顶表面并且包括形成在从浅沟槽隔离（STI）区域中选择的表面中的区域和具有与半导体衬底共面的外表面的掺杂阱的半导体衬底上形成MIM电容器。 电容器底板是形成在半导体衬底中的STI区域上的下电极或由可能具有硅化物表面的在半导体衬底的顶表面中形成的掺杂阱形成的下电极。 电容器HiK电介质层形成在下板上或上。 在电容器下板上方的HiK电介质层上形成电容器第二板。 可以在第二板的上方形成具有顶板的双电容器结构，其中通过侧壁间隔件连接到被第二板保护的下板的通孔。

公开(公告)号：US07732294B2

公开(公告)日：2010-06-08

申请号：US12170464

申请日：2008-07-10

申请人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

发明人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC分类号： H01L21/20

CPC分类号： H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of a semiconductor device. A substrate is provided. At least one metal wiring level is within the substrate. An insulative layer is deposited on a surface of the substrate. An inductor is formed within the insulative layer using a patterned plate process. A wire bond pad is formed within the insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

摘要翻译： 一种半导体器件的方法。 提供基板。 衬底内至少有一个金属布线层。 绝缘层沉积在衬底的表面上。 使用图案化板工艺在绝缘层内形成电感器。 在绝缘层内形成引线接合焊盘，其中引线接合焊盘的至少一部分与电感器基本上共面。

公开(公告)号：US20080293233A1

公开(公告)日：2008-11-27

申请号：US12170464

申请日：2008-07-10

申请人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

发明人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC分类号： H01L21/44

CPC分类号： H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of a semiconductor device. A substrate is provided. At least one metal wiring level is within the substrate. An insulative layer is deposited on a surface of the substrate. An inductor is formed within the insulative layer using a patterned plate process. A wire bond pad is formed within the insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

摘要翻译： 一种半导体器件的方法。 提供基板。 衬底内至少有一个金属布线层。 绝缘层沉积在衬底的表面上。 使用图案化板工艺在绝缘层内形成电感器。 在绝缘层内形成引线接合焊盘，其中引线接合焊盘的至少一部分与电感器基本上共面。

公开(公告)号：US07763954B2

公开(公告)日：2010-07-27

申请号：US12170489

申请日：2008-07-10

申请人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

发明人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC分类号： H01L29/00

CPC分类号： H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure. The semiconductor structure includes: a substrate having at least one metal wiring level within the substrate; an insulative layer on a surface of the substrate; an inductor within the insulative layer; and a wire bond pad within the insulative layer. The inductor and the wire bond pad are substantially co-planar. The inductor has a height greater than a height of the wire bond pad.

摘要翻译： 半导体结构。 半导体结构包括：在衬底内具有至少一个金属布线层的衬底; 在所述基板的表面上的绝缘层; 绝缘层内的电感器; 和绝缘层内的引线接合焊盘。 电感器和引线接合焊盘基本上是共面的。 电感器的高度大于引线接合焊盘的高度。

公开(公告)号：US07732295B2

公开(公告)日：2010-06-08

申请号：US12170473

申请日：2008-07-10

申请人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

发明人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC分类号： H01L21/20

CPC分类号： H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor substrate. A substrate is provided. At least one metal wiring level is within the substrate. A first insulative layer is deposited on a surface of the substrate. A portion of a wire bond pad is formed within the first insulative layer. A second insulative layer is deposited on the first insulative layer. An inductor is within the second insulative layer using a patterned plate process. A remaining portion of the wire bond pad is formed within the second insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

摘要翻译： 一种形成半导体衬底的方法。 提供基板。 衬底内至少有一个金属布线层。 第一绝缘层沉积在衬底的表面上。 引线接合焊盘的一部分形成在第一绝缘层内。 第二绝缘层沉积在第一绝缘层上。 电感器使用图案化板工艺在第二绝缘层内。 所述引线接合焊盘的剩余部分形成在所述第二绝缘层内，其中所述引线接合焊盘的至少一部分与所述电感器基本上共面。

公开(公告)号：US07573117B2

公开(公告)日：2009-08-11

申请号：US12174047

申请日：2008-07-16

申请人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

发明人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC分类号： H01L29/00

CPC分类号： H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above the substrate; an insulative layer on and above the capping layer; a first layer of photo-imagable material on and above the insulative layer; a layer of oxide on and above the first layer of photo-imagable material; a second layer of photo-imagable material on and above the layer of oxide; an inductor; and a wire bond pad. A first portion of the inductor is in the second layer of photo-imagable material, the layer of oxide, the first layer of photo-imagable material, the insulative layer, and the capping layer. A second portion of the inductor is in only the second layer of photo-imagable material. The wire bond pad in only the first layer of photo-imagable material, the insulative layer, and the capping layer.

摘要翻译： 半导体结构。 半导体结构包括：在衬底内具有金属布线层的衬底; 衬底上方的覆盖层; 覆盖层上方的绝缘层; 绝缘层上方的第一层可光成像材料; 第一层可光成像材料上方的氧化层; 位于氧化层上方的第二层可光成像材料; 电感; 和引线键合垫。 电感器的第一部分在第二层可光成像材料中，氧化层，第一层可光成像材料，绝缘层和封盖层。 电感器的第二部分仅在第二层可光成像材料中。 导线焊盘仅在第一层可光成像材料，绝缘层和封盖层中。

公开(公告)号：US20080290458A1

公开(公告)日：2008-11-27

申请号：US12170489

申请日：2008-07-10

申请人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

发明人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC分类号： H01L29/00

CPC分类号： H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure. The semiconductor structure includes: a substrate having at least one metal wiring level within the substrate; an insulative layer on a surface of the substrate; an inductor within the insulative layer; and a wire bond pad within the insulative layer. The inductor and the wire bond pad are substantially co-planar. The inductor has a height greater than a height of the wire bond pad.

摘要翻译： 半导体结构。 半导体结构包括：在衬底内具有至少一个金属布线层的衬底; 在所述基板的表面上的绝缘层; 绝缘层内的电感器; 和绝缘层内的引线接合焊盘。 电感器和引线接合焊盘基本上是共面的。 电感器的高度大于引线接合焊盘的高度。

公开(公告)号：US20080277759A1

公开(公告)日：2008-11-13

申请号：US12174020

申请日：2008-07-16

申请人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

发明人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC分类号： H01L29/00

CPC分类号： H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above a top surface of the substrate; an insulative layer on and above a top surface of the capping layer; an inductor comprising a first portion in and above the insulative layer and a second portion only above the insulative layer; and a wire bond pad within the insulative layer, wherein the first portion the inductor has a height in a first direction greater than a height of the wire bond pad in the first direction, wherein the first direction is perpendicularly directed from the top surface of substrate toward the insulative layer.

摘要翻译： 半导体结构。 半导体结构包括：在衬底内具有金属布线层的衬底; 在所述基板的顶表面上和上方的覆盖层; 在覆盖层的顶表面上和上方的绝缘层; 电感器，包括绝缘层中和上方的第一部分和仅在绝缘层上方的第二部分; 以及所述绝缘层内的引线接合焊盘，其中所述电感器的第一部分在第一方向上的高度大于所述引线接合焊盘在所述第一方向上的高度，其中所述第一方向垂直于所述基板的顶表面 朝向绝缘层。