公开(公告)号：US08255780B2

公开(公告)日：2012-08-28

申请号：US12708323

申请日：2010-02-18

申请人： Anindya Saha ,  Hemant Mallapur ,  Santhosh Billava ,  Smitha Banavikal Math Veerabhadresh

发明人： Anindya Saha ,  Hemant Mallapur ,  Santhosh Billava ,  Smitha Banavikal Math Veerabhadresh

IPC分类号： H03M13/03

CPC分类号： H03M13/4169 ,  H03M13/256 ,  H03M13/395 ,  H03M13/4107 ,  H03M13/6362

摘要： An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific processor includes a Load-Store, Logical and De-puncturing (LLD) slot that performs a Load-Store function, a Logical function, a De-puncturing function, and a Trace-back Address generation function, a Branch Metric Compute (BMU) slot that performs Radix-2 branch metric computations, Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations, and an Add-Compare-Select (ACS) slot that performs Radix-2 Path metric computations, Radix-4 Path metric computations, best state computations, and a decision bit generation. The LLD slot, the BMU slot and the ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.

摘要翻译： 一种应用专用处理器，用于实现用于接收符号的信道解码功能的维特比解码算法。 维特比解码算法是位串行解码算法和基于块的解码算法中的至少一种。 应用专用处理器包括执行加载存储功能的加载存储，逻辑和去穿孔（LLD）槽，逻辑功能，去穿孔功能和追踪地址生成功能，分支度量计算 （BMU）时隙，执行基数-2分支度量计算，基数-4分支度量计算和平方欧几里德分支度量计算，以及执行基数2路径度量计算的加法比较选择（ACS）时隙，基数-4 路径度量计算，最佳状态计算和决策位生成。 LLD插槽，BMU插槽和ACS插槽以软件流水线方式执行，以实现高速维特比解码功能。

公开(公告)号：US08447961B2

公开(公告)日：2013-05-21

申请号：US12708288

申请日：2010-02-18

申请人： Anindya Saha ,  Manish Kumar ,  Hemant Mallapur ,  Santhosh Billava ,  Viji Rajangam

发明人： Anindya Saha ,  Manish Kumar ,  Hemant Mallapur ,  Santhosh Billava ,  Viji Rajangam

IPC分类号： G06F9/40

CPC分类号： G06F9/325 ,  G06F9/30065 ,  G06F9/381 ,  G06F9/3853

摘要： A system to implement a zero overhead software pipelined (SFP) loop includes a Very Long Instruction Word (VLIW) processor having an N number of execution slots. The VLIW processor executes a plurality of instructions in parallel without any limitation of an instruction buffer size. A program memory receives a Program Memory address to fetch an instruction packet. The program memory is closely coupled with the instruction buffer size to implement the zero overhead software pipelined (SFP) loop. The size of the zero overhead software pipelined (SFP) loop can exceed the instruction buffer size. A CPU control register includes a block count and an iteration count. The block count is loaded into a block counter and counts the plurality of instructions executed in the SFP loop, and the iteration count is loaded into an iteration counter and counts a number of iterations of the SFP loop based on the block count.

摘要翻译： 实现零开销软件流水线（SFP）循环的系统包括具有N个执行时隙的超长指令字（VLIW）处理器。 VLIW处理器并行执行多个指令，而不受指令缓冲器大小的任何限制。 程序存储器接收程序存储器地址以获取指令包。 程序存储器与指令缓冲区大小紧密相连，以实现零开销软件流水线（SFP）循环。 零开销软件流水线（SFP）循环的大小可以超过指令缓冲区大小。 CPU控制寄存器包括块计数和迭代计数。 块计数被加载到块计数器中并对在SFP循环中执行的多个指令进行计数，并且将迭代计数加载到迭代计数器中，并且基于块计数对SFP循环的迭代次数进行计数。

公开(公告)号：US20100211762A1

公开(公告)日：2010-08-19

申请号：US12708288

申请日：2010-02-18

申请人： Anindya Saha ,  Manish Kumar ,  Hemant Mallapur ,  Santhosh Billava ,  Viji Rajangam

发明人： Anindya Saha ,  Manish Kumar ,  Hemant Mallapur ,  Santhosh Billava ,  Viji Rajangam

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/325 ,  G06F9/30065 ,  G06F9/381 ,  G06F9/3853

摘要： A system to implement a zero overhead software pipelined (SFP) loop includes a Very Long Instruction Word (VLIW) processor having an N number of execution slots. The VLIW processor executes a plurality of instructions in parallel without any limitation of an instruction buffer size. A program memory receives a Program Memory address to fetch an instruction packet. The program memory is closely coupled with the instruction buffer size to implement the zero overhead software pipelined (SFP) loop. The size of the zero overhead software pipelined (SFP) loop can exceed the instruction buffer size. A CPU control register includes a block count and an iteration count. The block count is loaded into a block counter and counts the plurality of instructions executed in the SFP loop, and the iteration count is loaded into an iteration counter and counts a number of iterations of the SFP loop based on the block count.

摘要翻译： 实现零开销软件流水线（SFP）循环的系统包括具有N个执行时隙的超长指令字（VLIW）处理器。 VLIW处理器并行执行多个指令，而不受指令缓冲器大小的任何限制。 程序存储器接收程序存储器地址以获取指令包。 程序存储器与指令缓冲区大小紧密相连，以实现零开销软件流水线（SFP）循环。 零开销软件流水线（SFP）循环的大小可以超过指令缓冲区大小。 CPU控制寄存器包括块计数和迭代计数。 块计数被加载到块计数器中并对在SFP循环中执行的多个指令进行计数，并且将迭代计数加载到迭代计数器中，并且基于块计数对SFP循环的迭代次数进行计数。

公开(公告)号：US20100211858A1

公开(公告)日：2010-08-19

申请号：US12708323

申请日：2010-02-18

申请人： Anindya Saha ,  Hemant Mallapur ,  Santhosh Billava ,  Smitha Bmv

发明人： Anindya Saha ,  Hemant Mallapur ,  Santhosh Billava ,  Smitha Bmv

IPC分类号： H03M13/25 ,  G06F15/76 ,  G06F15/80 ,  G06F9/02 ,  G06F11/08 ,  H03M13/41

CPC分类号： H03M13/4169 ,  H03M13/256 ,  H03M13/395 ,  H03M13/4107 ,  H03M13/6362

摘要： An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific processor includes a Load-Store, Logical and De-puncturing (LLD) slot that performs a Load-Store function, a Logical function, a De-puncturing function, and a Trace-back Address generation function, a Branch Metric Compute (BMU) slot that performs a Radix-2 branch metric computations, a Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations, and an Add-Compare-Select (ACS) slot that performs a Radix-2 Path metric computations, a Radix-4 Path metric computations, a best state computations, and a decision bit generation. The LLD slot, the BMU slot and the ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.

摘要翻译： 一种应用专用处理器，用于实现用于接收符号的信道解码功能的维特比解码算法。 维特比解码算法是位串行解码算法和基于块的解码算法中的至少一种。 应用专用处理器包括执行加载存储功能的加载存储，逻辑和去穿孔（LLD）槽，逻辑功能，去穿孔功能和追踪地址生成功能，分支度量计算 （BMU）时隙，执行基数-2分支度量计算，基数-4分支度量计算和平方欧几里德分支度量计算，以及执行基数2路径度量计算的加法比较选择（ACS） 基数4路径度量计算，最佳状态计算和决策位生成。 LLD插槽，BMU插槽和ACS插槽以软件流水线方式执行，以实现高速维特比解码功能。