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    Low swing flip-flop with reduced leakage slave latch
    1.
    发明授权
    Low swing flip-flop with reduced leakage slave latch 有权
    低摆幅触发器具有减少的漏电从器件锁存器

    公开(公告)号：US09425775B2

    公开(公告)日：2016-08-23

    申请号：US14481269

    申请日：2014-09-09

    Applicant: Anis M. Jarrar ,  John M. Dalbey ,  Alexander B. Hoefler ,  Colin MacDonald

    Inventor： Anis M. Jarrar ,  John M. Dalbey ,  Alexander B. Hoefler ,  Colin MacDonald

    IPC: H03K3/289 ,  H03K3/3562 ,  H03K3/037

    CPC classification number: H03K3/35625 ,  H03K3/0372

    Abstract: A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage.

    Abstract translation: 数据处理系统包括用于在第一和第二电压下提供功率的第一和第二配电网络以及触发器。 第二电压小于第一电压。 触发器包括具有连接到第一配电网络的电力节点的主锁存器，数据信号输入端和以第一电压驱动的输出信号输出，以及具有与第一电源连接的电源节点的从锁存器 配电网络，耦合到主锁存器的输出的输入，由第一电压驱动的从锁存器输出信号输出，以及具有与第二电压连接的功率节点的第一锁存逆变器的反馈电路，输入 耦合到主锁存器输出端，输出端提供由第二电压驱动的输出信号。

    LOW SWING FLIP-FLOP WITH REDUCED LEAKAGE SLAVE LATCH
    2.
    发明申请
    LOW SWING FLIP-FLOP WITH REDUCED LEAKAGE SLAVE LATCH 有权
    具有减少泄漏自动锁定的低开关翻转

    公开(公告)号：US20160072484A1

    公开(公告)日：2016-03-10

    申请号：US14481269

    申请日：2014-09-09

    Applicant: Anis M. Jarrar ,  John M. Dalbey ,  Alexander B. Hoefler ,  Colin MacDonald

    Inventor： Anis M. Jarrar ,  John M. Dalbey ,  Alexander B. Hoefler ,  Colin MacDonald

    IPC: H03K3/3562

    CPC classification number: H03K3/35625 ,  H03K3/0372

    Abstract: A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage.

    Abstract translation: 数据处理系统包括用于在第一和第二电压下提供功率的第一和第二配电网络以及触发器。 第二电压小于第一电压。 触发器包括具有连接到第一配电网络的电力节点的主锁存器，数据信号输入端和以第一电压驱动的输出信号输出，以及具有与第一电源连接的电源节点的从锁存器 配电网络，耦合到主锁存器的输出的输入，由第一电压驱动的从锁存输出信号输出，以及具有与第二电压连接的功率节点的第一锁存逆变器的反馈电路，输入 耦合到主锁存器输出端，输出端提供由第二电压驱动的输出信号。

    Dynamic timing adjustment in a circuit device
    3.
    发明授权
    Dynamic timing adjustment in a circuit device 有权
    电路设备中的动态时序调整

    公开(公告)号：US07716511B2

    公开(公告)日：2010-05-11

    申请号：US11371142

    申请日：2006-03-08

    Applicant: Anis M. Jarrar ,  Colin MacDonald

    Inventor： Anis M. Jarrar ,  Colin MacDonald

    IPC: G06F1/12 ,  H04L7/00

    CPC classification number: G06F1/10

    Abstract: A method includes determining a first operational characteristic representative of an operational speed of a circuit device at a first time. The method further includes receiving an input signal at an input of a first latch of the circuit device and receiving an output signal at an input of a second latch of the circuit device. The method additionally includes delaying a clock signal by a first delay to provide a first adjusted clock signal and delaying the clock signal by a second delay to provide a second adjusted clock signal. In one embodiment, the first delay and the second delay are based on the first operational characteristic. The method further includes latching the input signal at the first latch responsive to the first adjusted clock signal and latching the output signal at the second latch responsive to the second adjusted clock signal.

    Abstract translation: 一种方法包括在第一时间确定代表电路装置的操作速度的第一操作特性。 该方法还包括在电路装置的第一锁存器的输入处接收输入信号，并在电路装置的第二锁存器的输入处接收输出信号。 该方法还包括将时钟信号延迟第一延迟以提供第一调整时钟信号并延迟时钟信号第二延迟以提供第二调整时钟信号。 在一个实施例中，第一延迟和第二延迟基于第一操作特性。 该方法还包括响应于第一调整后的时钟信号而在第一锁存器处锁存输入信号，并响应于第二调整后的时钟信号将输出信号锁存在第二锁存器处。

    System and method for reducing the power consumption of clock systems
    4.
    发明授权
    System and method for reducing the power consumption of clock systems 有权
    降低时钟系统功耗的系统和方法

    公开(公告)号：US07418675B2

    公开(公告)日：2008-08-26

    申请号：US11342747

    申请日：2006-01-30

    Applicant: Colin MacDonald ,  John M. Dalbey ,  Anis M. Jarrar

    Inventor： Colin MacDonald ,  John M. Dalbey ,  Anis M. Jarrar

    IPC: G06F17/50

    CPC classification number: G06F17/5045 ,  G06F2217/62 ,  G06F2217/78

    Abstract: A system an method of designing an integrated circuit identifies a plurality of synchronous cells of an integrated circuit to be driven by a clock driver, wherein the plurality of synchronous cells are a subset of previously placed cells of the integrated circuit. The placement of synchronous cells is performed to reduce a current needed from the clock driver to drive the plurality of synchronous cells.

    Abstract translation: 一种设计集成电路的方法的系统识别由时钟驱动器驱动的集成电路的多个同步单元，其中多个同步单元是集成电路的先前放置的单元的子集。 执行同步单元的布置以减少从时钟驱动器驱动多个同步单元所需的电流。

    Dynamic timing adjustment in a circuit device
    5.
    发明申请
    Dynamic timing adjustment in a circuit device 有权
    电路设备中的动态时序调整

    公开(公告)号：US20070214377A1

    公开(公告)日：2007-09-13

    申请号：US11371142

    申请日：2006-03-08

    Applicant: Anis Jarrar ,  Colin MacDonald

    Inventor： Anis Jarrar ,  Colin MacDonald

    IPC: G06F1/12

    CPC classification number: G06F1/10

    Abstract: A method includes determining a first operational characteristic representative of an operational speed of a circuit device at a first time. The method further includes receiving an input signal at an input of a first latch of the circuit device and receiving an output signal at an input of a second latch of the circuit device. The method additionally includes delaying a clock signal by a first delay to provide a first adjusted clock signal and delaying the clock signal by a second delay to provide a second adjusted clock signal. In one embodiment, the first delay and the second delay are based on the first operational characteristic. The method further includes latching the input signal at the first latch responsive to the first adjusted clock signal and latching the output signal at the second latch responsive to the second adjusted clock signal.

    Abstract translation: 一种方法包括在第一时间确定代表电路装置的操作速度的第一操作特性。 该方法还包括在电路装置的第一锁存器的输入处接收输入信号，并在电路装置的第二锁存器的输入处接收输出信号。 该方法还包括将时钟信号延迟第一延迟以提供第一调整时钟信号并延迟时钟信号第二延迟以提供第二调整时钟信号。 在一个实施例中，第一延迟和第二延迟基于第一操作特性。 该方法还包括响应于第一调整后的时钟信号而在第一锁存器处锁存输入信号，并响应于第二调整后的时钟信号将输出信号锁存在第二锁存器处。

    Circuit and method of controlling cache memory
    6.
    发明授权
    Circuit and method of controlling cache memory 有权
    控制缓存的电路及方法

    公开(公告)号：US06279083B1

    公开(公告)日：2001-08-21

    申请号：US09275617

    申请日：1999-03-24

    Applicant: Colin MacDonald

    Inventor： Colin MacDonald

    IPC: G06F1200

    CPC classification number: G06F12/0888

    Abstract: A memory controller (26) compares the current address and the previous address sent by a microprocessor (12). If the addresses are DRAM addresses and the current row address matches the previous row address, i.e. same DRAM page access, then the memory controller disables caching (28) of the same DRAM page access. The same DRAM page access disables caching because the same DRAM page access is not substantially longer than a cache access. A counter (50) and comparator (52) allows the memory controller to hold off some number of same DRAM page accesses before disabling caching to give time for the memory controller to set up to the new page.

    Abstract translation: 存储器控制器（26）比较由微处理器（12）发送的当前地址和以前的地址。 如果地址是DRAM地址，并且当前行地址与先前的行地址相匹配，即相同的DRAM页访问，则存储器控制器禁用相同DRAM页访问的高速缓存（28）。 相同的DRAM页面访问禁用高速缓存，因为相同的DRAM页面访问不比缓存访问长得多。 计数器（50）和比较器（52）允许存储器控制器在禁用高速缓存之前暂停一些数量相同的DRAM页面访问，以给存储器控制器设置到新页面的时间。

    Method and system for transmitting data
    9.
    发明授权
    Method and system for transmitting data 有权
    发送数据的方法和系统

    公开(公告)号：US07378993B1

    公开(公告)日：2008-05-27

    申请号：US11619932

    申请日：2007-01-04

    Applicant: Colin MacDonald ,  Alan J. Carlin ,  Donald L. Tietjen

    Inventor： Colin MacDonald ,  Alan J. Carlin ,  Donald L. Tietjen

    IPC: H03M5/00

    CPC classification number: H03M5/145

    Abstract: A method and system for transmitting binary-coded data use partitioning of data words in a plurality of data nibbles. The data nibbles are coded using modified a 1-bit hot coding format that transforms a data nibble in a data segment including a plurality of bit groups. A change in a digital state at a bit position in a more significant bit group is maintained at that bit position in less significant bit groups, and information is transmitted in a form of a transition between digital states. The data segments are transmitted in phases each including one bit group from each data segment. At a receiving terminal, the bit groups are converted back in the binary-coded data words. In one application, the invention is used to reduce power consumption during data transmissions to and from an integrated circuit device.

    Abstract translation: 用于发送二进制编码数据的方法和系统使用多个数据半字节中的数据字的划分。 数据半字节使用修改的1位热编码格式进行编码，该格式转换包括多个位组的数据段中的数据半字节。 在较低有效位组中的位位置处，在更高有效位组中的位位置处的数字状态的变化保持在该位位置，并且以数字状态之间的转换的形式发送信息。 数据段以各自包括来自每个数据段的一个位组的相位传送。 在接收终端，以二进制编码数据字的形式转换位组。 在一个应用中，本发明用于降低与集成电路设备之间的数据传输期间的功耗。

    Image processing system with multiple processing units
    10.
    发明授权
    Image processing system with multiple processing units 失效
    具有多个处理单元的图像处理系统

    公开(公告)号：US06763150B1

    公开(公告)日：2004-07-13

    申请号：US09649927

    申请日：2000-08-29

    Applicant: Colin MacDonald

    Inventor： Colin MacDonald

    IPC: G06K954

    CPC classification number: H04N1/40 ,  H04N1/411

    Abstract: A circuit for processing a first image including two image supply blocks, two image processing units, a control unit and a plurality of buses. The image supply blocks assert selected lines of image data onto a respective one of first and second plurality of buses. The image processing units each process the data according to respective algorithms and provide respective update ok signals that each indicate that the respective image processing unit has completed use of the first sub-portion of data. The image supply blocks provide respective update signals to the image processing units in response to the update ok signals from both of the image processing units, transfer data from the second sub-portion to the first, and assert new data on the second sub-portion. Each image processing unit, in response to receiving both update signals, changes state to track the data without losing bus cycles to maintain performance.

    Abstract translation: 一种用于处理包括两个图像供应块，两个图像处理单元，一个控制单元和多个总线的第一图像的电路。 图像供应块将所选择的图像数据线插入第一和第二多个总线中的相应一个。 图像处理单元根据各自的算法对数据进行处理，并且提供各自的更新ok信号，每个更新ok信号各自指示相应的图像处理单元已经完成了数据的第一子部分的使用。 图像供给块响应于来自两个图像处理单元的更新ok信号向图像处理单元提供相应的更新信号，将数据从第二子部分传送到第一子部分，并且在第二子部分上断言新数据 。 每个图像处理单元响应于接收到两个更新信号而改变状态以跟踪数据而不会丢失总线周期以维持性能。

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