公开(公告)号：US20100061144A1

公开(公告)日：2010-03-11

申请号：US12206933

申请日：2008-09-09

申请人： Anosh B. Davierwalla ,  Cheng Zhong ,  Dongkyu Park ,  Mohamed Hassan Abu-Rahma ,  Mehdi Hamidi Sani ,  Sei Seung Yoon

发明人： Anosh B. Davierwalla ,  Cheng Zhong ,  Dongkyu Park ,  Mohamed Hassan Abu-Rahma ,  Mehdi Hamidi Sani ,  Sei Seung Yoon

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C11/1673

摘要： In a particular embodiment, a memory device is disclosed that includes a memory cell including a resistance-based memory element coupled to an access transistor. The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier configured to couple the memory cell to a supply voltage that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.

摘要翻译： 在特定实施例中，公开了一种存储器件，其包括存储单元，该存储单元包括耦合到存取晶体管的基于电阻的存储元件。 存取晶体管具有第一氧化物厚度，以使得能够在工作电压下操作存储单元。 存储器件还包括第一放大器，其被配置为将存储器单元耦合到大于电压限制的电源电压，以基于通过存储器单元的电流来产生数据信号。 第一放大器包括具有大于第一氧化物厚度的第二氧化物厚度的钳位晶体管。 钳位晶体管被配置为防止存储器单元处的工作电压超过电压限制。

公开(公告)号：US08228714B2

公开(公告)日：2012-07-24

申请号：US12206933

申请日：2008-09-09

申请人： Anosh B. Davierwalla ,  Cheng Zhong ,  Dongkyu Park ,  Mohamed Hassan Abu-Rahma ,  Mehdi Hamidi Sani ,  Sei Seung Yoon

发明人： Anosh B. Davierwalla ,  Cheng Zhong ,  Dongkyu Park ,  Mohamed Hassan Abu-Rahma ,  Mehdi Hamidi Sani ,  Sei Seung Yoon

IPC分类号： G11C11/00

CPC分类号： G11C11/1673

摘要： In a particular embodiment, a memory device is disclosed that includes a memory cell including a resistance-based memory element coupled to an access transistor. The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier configured to couple the memory cell to a supply voltage that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.

摘要翻译： 在特定实施例中，公开了一种存储器件，其包括存储单元，该存储单元包括耦合到存取晶体管的基于电阻的存储元件。 存取晶体管具有第一氧化物厚度，以使得能够在工作电压下操作存储单元。 存储器件还包括第一放大器，其被配置为将存储器单元耦合到大于电压限制的电源电压，以基于通过存储器单元的电流来产生数据信号。 第一放大器包括具有大于第一氧化物厚度的第二氧化物厚度的钳位晶体管。 钳位晶体管被配置为防止存储器单元处的工作电压超过电压限制。

公开(公告)号：US20100157654A1

公开(公告)日：2010-06-24

申请号：US12338297

申请日：2008-12-18

申请人： Seong-Ook Jung ,  Jisu Kim ,  Jee-Hwan Song ,  Seung H. Kang ,  Sei Seung Yoon ,  Mehdi Hamidi Sani

发明人： Seong-Ook Jung ,  Jisu Kim ,  Jee-Hwan Song ,  Seung H. Kang ,  Sei Seung Yoon ,  Mehdi Hamidi Sani

IPC分类号： G11C11/00 ,  G11C11/14 ,  G11C7/00 ,  G11C7/06

CPC分类号： G11C7/14 ,  G11C7/12 ,  G11C11/1673

摘要： A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure. The bit line is adapted to detect data having a logic one value when the bit line has a first voltage value, and to detect data having a logic zero value when the bit line has a second voltage value. The circuit further includes a second transistor load of a reference cell. The second transistor load is coupled to the first transistor load, and the second transistor load has an associated reference voltage value. A characteristic of the first transistor load, such as transistor width, is adjustable to modify the first voltage value and the second voltage value without substantially changing the reference voltage value.

摘要翻译： 公开了一种基于电阻的存储器电路。 电路包括数据单元的第一晶体管负载和适于检测第一逻辑状态的位线。 位线耦合到第一晶体管负载并耦合到具有磁隧道结（MTJ）结构的数据单元。 当位线具有第一电压值时，位线适于检测具有逻辑1值的数据，并且当位线具有第二电压值时检测具有逻辑零值的数据。 电路还包括参考单元的第二晶体管负载。 第二晶体管负载耦合到第一晶体管负载，并且第二晶体管负载具有相关联的参考电压值。 第一晶体管负载（例如晶体管宽度）的特性是可调节的，以修改第一电压值和第二电压值，而基本上不改变参考电压值。

公开(公告)号：US20100110775A1

公开(公告)日：2010-05-06

申请号：US12265044

申请日：2008-11-05

申请人： Sei Seung Yoon ,  Mehdi Hamidi Sani ,  Seung H. Kang

发明人： Sei Seung Yoon ,  Mehdi Hamidi Sani ,  Seung H. Kang

IPC分类号： G11C11/02 ,  G11C8/08 ,  G11C11/00 ,  G11C7/00

CPC分类号： G11C8/08 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： Systems, circuits and methods for controlling the word line voltage applied to word line transistors in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor. The bit cell is coupled to a bit line and a source line. A word line driver is coupled to a gate of the word line transistor. The word line driver is configured to provide a word line voltage greater than a supply voltage below a transition voltage of the supply voltage and to provide a voltage less than the supply voltage for supply voltages above the transition voltage.

摘要翻译： 公开了用于控制施加到自旋转移力矩随机存取存储器（STT-MRAM）中的字线晶体管的字线电压的系统，电路和方法。 一个实施例涉及包括具有磁性隧道结（MTJ）和字线晶体管的比特单元的STT-MRAM。 位单元耦合到位线和源极线。 字线驱动器耦合到字线晶体管的栅极。 字线驱动器被配置为提供大于低于电源电压的转换电压的电源电压的字线电压，并且为电压高于转换电压提供小于电源电压的电压。

公开(公告)号：US08144509B2

公开(公告)日：2012-03-27

申请号：US12163359

申请日：2008-06-27

申请人： Seong-Ook Jung ,  Mehdi Hamidi Sani ,  Seung H. Kang ,  Sei Seung Yoon

发明人： Seong-Ook Jung ,  Mehdi Hamidi Sani ,  Seung H. Kang ,  Sei Seung Yoon

IPC分类号： G11C11/14

CPC分类号： G11C11/1675 ,  G11C8/12 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1693 ,  Y10S977/933

摘要： Systems, circuits and methods for controlling write operations in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A reduced bit cell size is achieved by arranging the source lines (SL) substantially in parallel with the word lines (WL) and substantially perpendicular to the bit lines (BL). Further, in one embodiment during a write operation, a high logic/voltage level is applied to the bit lines of unselected bit cells to prevent an invalid write operation.

摘要翻译： 公开了用于控制旋转转矩磁阻随机存取存储器（STT-MRAM）中的写入操作的系统，电路和方法。 通过将源极线（SL）基本上与字线（WL）平行布置并且基本上垂直于位线（BL）来实现降低的位单元尺寸。 此外，在一个实施例中，在写入操作期间，高逻辑/电压电平被施加到未选择的位单元的位线，以防止无效的写入操作。

公开(公告)号：US20080247222A1

公开(公告)日：2008-10-09

申请号：US11972674

申请日：2008-01-11

申请人： Seong-Ook Jung ,  Seung H. Kang ,  Sei Seung Yoon ,  Mehdi Hamidi Sani

发明人： Seong-Ook Jung ,  Seung H. Kang ,  Sei Seung Yoon ,  Mehdi Hamidi Sani

IPC分类号： G11C11/00 ,  G06F17/50

CPC分类号： G11C11/1675 ,  G11C11/1659 ,  G11C11/1673

摘要： Systems, circuits and methods for determining read and write voltages for a given word line transistor in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A first voltage can be supplied to the write operations so that the write operations occur in the saturation region of the word line transistor. A second voltage, which is less than the first voltage, can be supplied for read operations so that the read operations occur in the linear region of the word line transistor.

摘要翻译： 公开了用于确定自旋转移磁阻随机存取存储器（STT-MRAM）中给定字线晶体管的读和写电压的系统，电路和方法。 可以向写入操作提供第一电压，使得写入操作发生在字线晶体管的饱和区域中。 可以提供小于第一电压的第二电压用于读取操作，使得读取操作发生在字线晶体管的线性区域中。

公开(公告)号：US07889585B2

公开(公告)日：2011-02-15

申请号：US12338297

申请日：2008-12-18

申请人： Seong-Ook Jung ,  Jisu Kim ,  Jee-Hwan Song ,  Seung H. Kang ,  Sei Seung Yoon ,  Mehdi Hamidi Sani

发明人： Seong-Ook Jung ,  Jisu Kim ,  Jee-Hwan Song ,  Seung H. Kang ,  Sei Seung Yoon ,  Mehdi Hamidi Sani

IPC分类号： G11C7/00

CPC分类号： G11C7/14 ,  G11C7/12 ,  G11C11/1673

摘要： A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure. The bit line is adapted to detect data having a logic one value when the bit line has a first voltage value, and to detect data having a logic zero value when the bit line has a second voltage value. The circuit further includes a second transistor load of a reference cell. The second transistor load is coupled to the first transistor load, and the second transistor load has an associated reference voltage value. A characteristic of the first transistor load, such as transistor width, is adjustable to modify the first voltage value and the second voltage value without substantially changing the reference voltage value.

摘要翻译： 公开了一种基于电阻的存储器电路。 电路包括数据单元的第一晶体管负载和适于检测第一逻辑状态的位线。 位线耦合到第一晶体管负载并耦合到具有磁隧道结（MTJ）结构的数据单元。 当位线具有第一电压值时，位线适于检测具有逻辑1值的数据，并且当位线具有第二电压值时检测具有逻辑零值的数据。 电路还包括参考单元的第二晶体管负载。 第二晶体管负载耦合到第一晶体管负载，并且第二晶体管负载具有相关联的参考电压值。 第一晶体管负载（例如晶体管宽度）的特性是可调节的，以修改第一电压值和第二电压值，而基本上不改变参考电压值。

公开(公告)号：US08107280B2

公开(公告)日：2012-01-31

申请号：US12265044

申请日：2008-11-05

申请人： Sei Seung Yoon ,  Mehdi Hamidi Sani ,  Seung H. Kang

发明人： Sei Seung Yoon ,  Mehdi Hamidi Sani ,  Seung H. Kang

IPC分类号： G11C11/00 ,  G11C11/14 ,  G11C11/15 ,  G11C8/00

CPC分类号： G11C8/08 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： Systems, circuits and methods for controlling the word line voltage applied to word line transistors in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor. The bit cell is coupled to a bit line and a source line. A word line driver is coupled to a gate of the word line transistor. The word line driver is configured to provide a word line voltage greater than a supply voltage below a transition voltage of the supply voltage and to provide a voltage less than the supply voltage for supply voltages above the transition voltage.

摘要翻译： 公开了用于控制施加到自旋转移力矩随机存取存储器（STT-MRAM）中的字线晶体管的字线电压的系统，电路和方法。 一个实施例涉及包括具有磁性隧道结（MTJ）和字线晶体管的比特单元的STT-MRAM。 位单元耦合到位线和源极线。 字线驱动器耦合到字线晶体管的栅极。 字线驱动器被配置为提供大于低于电源电压的转换电压的电源电压的字线电压，并且为电压高于转换电压提供小于电源电压的电压。

公开(公告)号：US07764537B2

公开(公告)日：2010-07-27

申请号：US11972674

申请日：2008-01-11

申请人： Seong-Ook Jung ,  Seung H. Kang ,  Sei Seung Yoon ,  Mehdi Hamidi Sani

发明人： Seong-Ook Jung ,  Seung H. Kang ,  Sei Seung Yoon ,  Mehdi Hamidi Sani

IPC分类号： G11C11/00

CPC分类号： G11C11/1675 ,  G11C11/1659 ,  G11C11/1673

摘要： Systems, circuits and methods for determining read and write voltages for a given word line transistor in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A first voltage can be supplied to the write operations so that the write operations occur in the saturation region of the word line transistor. A second voltage, which is less than the first voltage, can be supplied for read operations so that the read operations occur in the linear region of the word line transistor.

摘要翻译： 公开了用于确定自旋转移磁阻随机存取存储器（STT-MRAM）中给定字线晶体管的读和写电压的系统，电路和方法。 可以向写入操作提供第一电压，使得写入操作发生在字线晶体管的饱和区域中。 可以提供小于第一电压的第二电压用于读取操作，使得读取操作发生在字线晶体管的线性区域中。

公开(公告)号：US20090323404A1

公开(公告)日：2009-12-31

申请号：US12163359

申请日：2008-06-27

申请人： Seong-Ook Jung ,  Mehdi Hamidi Sani ,  Seung H. Kang ,  Sei Seung Yoon

发明人： Seong-Ook Jung ,  Mehdi Hamidi Sani ,  Seung H. Kang ,  Sei Seung Yoon

IPC分类号： G11C11/00

CPC分类号： G11C11/1675 ,  G11C8/12 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1693 ,  Y10S977/933

摘要： Systems, circuits and methods for controlling write operations in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A reduced bit cell size is achieved by arranging the source lines (SL) substantially in parallel with the word lines (WL) and substantially perpendicular to the bit lines (BL). Further, in one embodiment during a write operation, a high logic/voltage level is applied to the bit lines of unselected bit cells to prevent an invalid write operation.

摘要翻译： 公开了用于控制旋转转矩磁阻随机存取存储器（STT-MRAM）中的写入操作的系统，电路和方法。 通过将源极线（SL）基本上与字线（WL）平行布置并且基本上垂直于位线（BL）来实现降低的位单元尺寸。 此外，在一个实施例中，在写入操作期间，高逻辑/电压电平被施加到未选择的位单元的位线，以防止无效的写入操作。