公开(公告)号：US20060095751A1

公开(公告)日：2006-05-04

申请号：US10946465

申请日：2004-09-20

申请人： Anthony Bybell ,  Richard Doing ,  David Dukro

发明人： Anthony Bybell ,  Richard Doing ,  David Dukro

IPC分类号： G06F9/44

CPC分类号： G06F8/443

摘要： A method and system for reducing overhead on a loop of a plurality of instructions is disclosed. The loop is performed a particular number of times. The method and system include a mask register and addition logic. The mask register provides a carry mask having a first value for the loop being performed at least the particular number of times minus one time and a second value for at least a last instruction of the loop being performed a last time. The addition logic is coupled with the mask register and determines which of the plurality of instructions is to be executed. The carry mask and a current instruction of the plurality of instructions correspond to inputs of the addition logic. A resultant of the addition logic corresponds to a next instruction of the plurality of instructions unless the current instruction is the last instruction. The resultant of the addition logic corresponds to the first instruction if the current instruction is the last instruction and the loop is being performed less than the particular number of times.

摘要翻译： 公开了一种用于减少多个指令的循环上的开销的方法和系统。 循环执行特定次数。 该方法和系统包括掩码寄存器和加法逻辑。 屏蔽寄存器提供进位掩码，该进位掩码具有至少在特定次数减去一次的循环中执行的第一值，以及最后一次执行循环的至少最后指令的第二值。 加法逻辑与屏蔽寄存器耦合，并确定要执行多个指令中的哪一个。 多个指令中的进位掩码和当前指令对应于加法逻辑的输入。 加法逻辑的结果对应于多个指令中的下一指令，除非当前指令是最后指令。 如果当前指令是最后一条指令并且循环正在执行小于特定次数，则加法逻辑的结果对应于第一指令。

公开(公告)号：US20050216703A1

公开(公告)日：2005-09-29

申请号：US10810235

申请日：2004-03-26

申请人： James Dieffenderfer ,  Richard Doing ,  Brian Stempel ,  Steven Testa ,  Kenichi Tsuchiya

发明人： James Dieffenderfer ,  Richard Doing ,  Brian Stempel ,  Steven Testa ,  Kenichi Tsuchiya

IPC分类号： G06F9/38 ,  G06F9/40

CPC分类号： G06F9/3842 ,  G06F9/3861 ,  G06F9/3867

摘要： A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.

摘要翻译： 一种用于在流水线处理器中执行指令的方法和装置。 由于执行分支校正，或当中断改变指令流的序列时，该方法减少了在处理流中发生气泡时指令高速缓存和流水线处理器之间的等待时间。 当用于检测分支预测的解码级和相关指令队列位置具有表示处理流中的气泡的无效数据时，等待时间减少。 执行指令并行插入到解码级和指令队列中，从而将流水线级的长度减少一个周期。

公开(公告)号：US20070118837A1

公开(公告)日：2007-05-24

申请号：US11284257

申请日：2005-11-21

申请人： Richard Doing ,  John Patty ,  Steven Testa ,  Thuong Truong

发明人： Richard Doing ,  John Patty ,  Steven Testa ,  Thuong Truong

IPC分类号： G06F9/46

CPC分类号： G06F9/524

摘要： A method, and apparatus are provided for preventing livelocks in processor selection of load requests in a multiprocessor (MP) system. On random occasions a selection mechanism is changed for first holding up all requests and then a random selection is made. Then a round robin selection mechanism is used for further requests. A livelock-preventing selection mechanism includes a pair of linear feedback shift registers (LFSRs), each LFSR for generating pseudo random values.

摘要翻译： 提供了一种用于在多处理器（MP）系统中防止处理器选择负载请求中的活动锁定的方法和装置。 在随机的情况下，改变选择机制以首先保持所有请求，然后进行随机选择。 然后轮询选择机制用于进一步的请求。 防锁选择机构包括一对线性反馈移位寄存器（LFSR），每个LFSR用于产生伪随机值。

公开(公告)号：US20060155961A1

公开(公告)日：2006-07-13

申请号：US11030339

申请日：2005-01-06

申请人： James Dieffenderfer ,  Richard Doing ,  Sanjay Patel ,  Steven Testa ,  Kenichi Tsuchiya

发明人： James Dieffenderfer ,  Richard Doing ,  Sanjay Patel ,  Steven Testa ,  Kenichi Tsuchiya

IPC分类号： G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/382

摘要： Method and apparatus for reformatting instructions in a pipelined processor. An instruction register holds a plurality of instructions received from a cache memory external to the processor. A predecoder predecodes each of the instructions and determines from an instruction operation field where the instruction fields should be placed. A multiplexer reformats architecturally aligned instructions into hardware implementation aligned instructions prior to storing into L1 cache, so that the instructions are ready for dispatch to the pipeline execution units.

摘要翻译： 用于在流水线处理器中重新格式化指令的方法和装置。 指令寄存器保存从处理器外部的高速缓冲存储器接收的多个指令。 预解码器对每个指令进行预解码，并从指令操作字段中确定应放置指令字段。 多路复用器将结构化对齐的指令重新格式化为在存储到L1高速缓存之前的硬件实现对准的指令，使得指令准备好发送到流水线执行单元。

公开(公告)号：US20060236080A1

公开(公告)日：2006-10-19

申请号：US11109001

申请日：2005-04-19

申请人： Richard Doing ,  Brett Olsson ,  Kenichi Tsuchiya

发明人： Richard Doing ,  Brett Olsson ,  Kenichi Tsuchiya

IPC分类号： G06F15/00

CPC分类号： G06F9/3804 ,  G06F9/3844

摘要： A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.

摘要翻译： 一种用于减少预测的分支指令的目标指令的获取时间的方法和处理器。 缓冲器中的每个条目（这里称为“分支目标缓冲器”）可以存储预测的分支指令的地址和从预测的分支指令的目标地址开始的指令。 当从指令高速缓存中取出指令时，使用获取的指令的特定位来对分支目标缓冲器中的特定条目进行索引。 将索引条目中的分支指令的地址与从指令高速缓存获取的指令的地址进行比较。 如果有匹配，则从该分支指令的目标地址开始的指令直接在分支指令的后面进行调度。 以这种方式，减少预测的分支指令的目标指令的获取时间。

公开(公告)号：US20060036811A1

公开(公告)日：2006-02-16

申请号：US10915982

申请日：2004-08-11

申请人： James Dieffenderfer ,  Richard Doing ,  Brian Frankel ,  Kenichi Tsuchiya

发明人： James Dieffenderfer ,  Richard Doing ,  Brian Frankel ,  Kenichi Tsuchiya

IPC分类号： G06F12/00

CPC分类号： G06F12/126 ,  G06F12/125

摘要： An LRU array and method for tracking the accessing of lines of an associative cache. The most recently accessed lines of the cache are identified in the table, and cache lines can be blocked from being replaced. The LRU array contains a data array having a row of data representing each line of the associative cache, having a common address portion. A first set of data for the cache line identifies the relative age of the cache line for each way with respect to every other way. A second set of data identifies whether a line of one of the ways is not to be replaced. For cache line replacement, the cache controller will select the least recently accessed line using contents of the LRU array, considering the value of the first set of data, as well as the value of the second set of data indicating whether or not a way is locked. Updates to the LRU occur after each pre-fetch or fetch of a line or when it replaces another line in the cache memory.

摘要翻译： 用于跟踪关联高速缓存行的访问的LRU数组和方法。 缓存中最近访问的行在表中标识，并且可以阻止缓存行被替换。 LRU阵列包含具有代表相关高速缓存的每行的数据行的数据阵列，其具有公共地址部分。 高速缓存行的第一组数据相对于每隔一个方式识别每个方式的高速缓存行的相对年龄。 第二组数据识别一条路线是否不被替换。 对于高速缓存行替换，高速缓存控制器将使用LRU阵列的内容来选择最近访问的行，考虑第一组数据的值，以及第二组数据的值，指示一种方式是否为 锁定 对LRU的更新发生在每个预取或提取行之后，或者替换高速缓存中的另一行时。

公开(公告)号：US20050091476A1

公开(公告)日：2005-04-28

申请号：US10948776

申请日：2004-09-23

申请人： Richard Doing ,  Ronald Kalla ,  Stephen Schwinn ,  Edward Silha ,  Kenichi Tsuchiya

发明人： Richard Doing ,  Ronald Kalla ,  Stephen Schwinn ,  Edward Silha ,  Kenichi Tsuchiya

IPC分类号： G06F9/38 ,  G06F12/02 ,  G06F12/10 ,  G06F12/14 ,  G06F15/00

CPC分类号： G06F9/3804 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/5077 ,  G06F12/0284 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/1491

摘要： A processor supports logical partitioning of hardware resources including real address spaces of a computer system. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions and can dynamically re-allocate resources. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, and is capable of entering hypervisor state only upon occurrence of certain pre-defined events. A logical partition identifier is stored in a processor register, and can be altered by the processor only when in hypervisor state. Certain bus communications contain a logical partition identifier tag, and the processor ignores such communications if the tag does not match its own logical partition identifier in its register.

摘要翻译： 处理器支持包括计算机系统的真实地址空间的硬件资源的逻辑分区。 一个超级特权的管理程序称为虚拟机管理程序，可以调节逻辑分区，并可以动态重新分配资源。 优选地，处理器支持硬件多线程，每个线程独立地能够处于管理程序，管理程序或问题状态中，并且仅在某些预定义事件发生时能够进入管理程序状态。 逻辑分区标识符存储在处理器寄存器中，并且只有处于管理程序状态时才能被处理器改变。 某些总线通信包含逻辑分区标识符标签，如果标记与其寄存器中的自己的逻辑分区标识符不匹配，则处理器忽略此类通信。