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1.发明申请Method for software controllable dynamically lockable cache line replacement system 有权软件可控动态锁定缓存线替换系统的方法公开(公告)号：US20060036811A1
公开(公告)日：2006-02-16
申请号：US10915982
申请日：2004-08-11
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/125
摘要： An LRU array and method for tracking the accessing of lines of an associative cache. The most recently accessed lines of the cache are identified in the table, and cache lines can be blocked from being replaced. The LRU array contains a data array having a row of data representing each line of the associative cache, having a common address portion. A first set of data for the cache line identifies the relative age of the cache line for each way with respect to every other way. A second set of data identifies whether a line of one of the ways is not to be replaced. For cache line replacement, the cache controller will select the least recently accessed line using contents of the LRU array, considering the value of the first set of data, as well as the value of the second set of data indicating whether or not a way is locked. Updates to the LRU occur after each pre-fetch or fetch of a line or when it replaces another line in the cache memory.
摘要翻译： 用于跟踪关联高速缓存行的访问的LRU数组和方法。 缓存中最近访问的行在表中标识，并且可以阻止缓存行被替换。 LRU阵列包含具有代表相关高速缓存的每行的数据行的数据阵列，其具有公共地址部分。 高速缓存行的第一组数据相对于每隔一个方式识别每个方式的高速缓存行的相对年龄。 第二组数据识别一条路线是否不被替换。 对于高速缓存行替换，高速缓存控制器将使用LRU阵列的内容来选择最近访问的行，考虑第一组数据的值，以及第二组数据的值，指示一种方式是否为 锁定 对LRU的更新发生在每个预取或提取行之后，或者替换高速缓存中的另一行时。
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2.发明申请Apparatus and method for reformatting instructions before reaching a dispatch point in a superscalar processor 审中-公开在超标量处理器到达调度点之前重新格式化指令的装置和方法公开(公告)号：US20060155961A1
公开(公告)日：2006-07-13
申请号：US11030339
申请日：2005-01-06
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/382
摘要： Method and apparatus for reformatting instructions in a pipelined processor. An instruction register holds a plurality of instructions received from a cache memory external to the processor. A predecoder predecodes each of the instructions and determines from an instruction operation field where the instruction fields should be placed. A multiplexer reformats architecturally aligned instructions into hardware implementation aligned instructions prior to storing into L1 cache, so that the instructions are ready for dispatch to the pipeline execution units.
摘要翻译： 用于在流水线处理器中重新格式化指令的方法和装置。 指令寄存器保存从处理器外部的高速缓冲存储器接收的多个指令。 预解码器对每个指令进行预解码，并从指令操作字段中确定应放置指令字段。 多路复用器将结构化对齐的指令重新格式化为在存储到L1高速缓存之前的硬件实现对准的指令，使得指令准备好发送到流水线执行单元。
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3.发明申请Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor 失效用于减少指令高速缓存和流水线处理器之间的等待时间的装置和方法公开(公告)号：US20050216703A1
公开(公告)日：2005-09-29
申请号：US10810235
申请日：2004-03-26
CPC分类号： G06F9/3842 , G06F9/3861 , G06F9/3867
摘要： A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.
摘要翻译： 一种用于在流水线处理器中执行指令的方法和装置。 由于执行分支校正，或当中断改变指令流的序列时，该方法减少了在处理流中发生气泡时指令高速缓存和流水线处理器之间的等待时间。 当用于检测分支预测的解码级和相关指令队列位置具有表示处理流中的气泡的无效数据时，等待时间减少。 执行指令并行插入到解码级和指令队列中，从而将流水线级的长度减少一个周期。
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4.发明申请Reducing the fetch time of target instructions of a predicted taken branch instruction 失效减少预测的分支指令的目标指令的获取时间公开(公告)号：US20060236080A1
公开(公告)日：2006-10-19
申请号：US11109001
申请日：2005-04-19
申请人： Richard Doing , Brett Olsson , Kenichi Tsuchiya
发明人： Richard Doing , Brett Olsson , Kenichi Tsuchiya
IPC分类号： G06F15/00
CPC分类号： G06F9/3804 , G06F9/3844
摘要： A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.
摘要翻译： 一种用于减少预测的分支指令的目标指令的获取时间的方法和处理器。 缓冲器中的每个条目（这里称为“分支目标缓冲器”）可以存储预测的分支指令的地址和从预测的分支指令的目标地址开始的指令。 当从指令高速缓存中取出指令时，使用获取的指令的特定位来对分支目标缓冲器中的特定条目进行索引。 将索引条目中的分支指令的地址与从指令高速缓存获取的指令的地址进行比较。 如果有匹配，则从该分支指令的目标地址开始的指令直接在分支指令的后面进行调度。 以这种方式，减少预测的分支指令的目标指令的获取时间。
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公开(公告)号：US20050091476A1
公开(公告)日：2005-04-28
申请号：US10948776
申请日：2004-09-23
申请人： Richard Doing , Ronald Kalla , Stephen Schwinn , Edward Silha , Kenichi Tsuchiya
发明人： Richard Doing , Ronald Kalla , Stephen Schwinn , Edward Silha , Kenichi Tsuchiya
CPC分类号： G06F9/3804 , G06F9/3842 , G06F9/3851 , G06F9/5077 , G06F12/0284 , G06F12/1036 , G06F12/109 , G06F12/1491
摘要： A processor supports logical partitioning of hardware resources including real address spaces of a computer system. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions and can dynamically re-allocate resources. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, and is capable of entering hypervisor state only upon occurrence of certain pre-defined events. A logical partition identifier is stored in a processor register, and can be altered by the processor only when in hypervisor state. Certain bus communications contain a logical partition identifier tag, and the processor ignores such communications if the tag does not match its own logical partition identifier in its register.
摘要翻译： 处理器支持包括计算机系统的真实地址空间的硬件资源的逻辑分区。 一个超级特权的管理程序称为虚拟机管理程序，可以调节逻辑分区，并可以动态重新分配资源。 优选地，处理器支持硬件多线程，每个线程独立地能够处于管理程序，管理程序或问题状态中，并且仅在某些预定义事件发生时能够进入管理程序状态。 逻辑分区标识符存储在处理器寄存器中，并且只有处于管理程序状态时才能被处理器改变。 某些总线通信包含逻辑分区标识符标签，如果标记与其寄存器中的自己的逻辑分区标识符不匹配，则处理器忽略此类通信。
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公开(公告)号：US08235879B2
公开(公告)日：2012-08-07
申请号：US12141369
申请日：2008-06-18
IPC分类号： F16C13/00
CPC分类号： G03G15/0233
摘要： A charging roll includes a shaft and an ionically conductive elastic layer formed around the shaft. The ionically conductive elastic layer is formed of a rubber composition free of any electron-conductive agent and containing 0.7 to 1.0 parts by weight of a peroxide cross-linking agent per 100 parts by weight of an ion-conductive rubber. The ion-conductive rubber is formed of at least one of an epichlorohydrin rubber and a nitrile rubber, and a percentage of a rubber component in the ionically conductive elastic layer measured by thermogravimetric analysis is 90% or more by weight.
摘要翻译： 充电辊包括轴和形成在轴周围的离子导电弹性层。 离子导电弹性层由不含任何电子传导剂的橡胶组合物形成，并且每100重量份的离子传导橡胶含有0.7-1.0重量份的过氧化物交联剂。 离子导电橡胶由表氯醇橡胶和丁腈橡胶中的至少一种形成，并且通过热重分析测定的离子导电性弹性层中的橡胶成分的百分比为90重量％以上。
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7.发明授权Portable television-broadcast reception unit, television-broadcast reception method, television-broadcast reception program, and computer-readable record medium with television-broadcast reception program 有权便携式电视广播接收单元，电视广播接收方式，电视广播接收节目以及具有电视广播接收节目的计算机可读记录介质公开(公告)号：US07978269B2
公开(公告)日：2011-07-12
申请号：US11630834
申请日：2006-04-25
CPC分类号： H01Q1/1257 , H04N5/44 , H04N21/41407 , H04N21/44209
摘要： A portable television-broadcast reception unit is provided which is capable of changing the direction of a directional antenna easily to a direction where an enough quality to watch television can be obtained. In this unit: a television-broadcast reception section 20 receives a broadcast wave using a directional antenna 10; a direction measurement section 60 measures the direction of the directional antenna 10; an electric-field strength measurement section 70 measures the electric-field strength value of the received broadcast wave; a storage section 30 stores an electric-field strength management table which includes the direction measured by the direction measurement section 60 and the electric-field strength value measured by the electric-field strength measurement section 70; a control section 40 controls the measurement of the direction and the measurement of the electric-field strength, updates the electric-field strength management table and selects the direction where the maximum electric-field strength value can be obtained; an image-turn processing section 80 turns the received image so that the upper part of the image is oriented to the direction where the maximum electric-field strength value can be obtained; and a display section 50 displays the turned image.
摘要翻译： 提供了便携式电视广播接收单元，其能够容易地将定向天线的方向改变为能够获得足够的观看电视质量的方向。 在该单元中：电视广播接收部分20使用定向天线10接收广播波; 方向测量部分60测量定向天线10的方向; 电场强度测量部分70测量所接收的广播波的电场强度值; 存储部分30存储包括由方向测量部分60测量的方向和由电场强度测量部分70测量的电场强度值的电场强度管理表; 控制部分40控制电场强度的方向和测量的测量，更新电场强度管理表并选择可以获得最大电场强度值的方向; 图像转弯处理部80转动接收图像，使得图像的上部朝向能够获得最大电场强度值的方向; 显示部50显示转动后的图像。
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公开(公告)号：US20090116323A1
公开(公告)日：2009-05-07
申请号：US12349652
申请日：2009-01-07
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces the need to write complex testing software. Higher level functions may be inserted between the shadow latches and the addressing latches to automatically provide functions such as inversions.
摘要翻译： 公开了一种用于多功能时钟速度连续扫描阵列内置自检（ABIST）多端口存储器的系统。 在ABIST测试期间，来自第一端口的功能寻址锁存器用作第二端口寻址锁存器的阴影锁存器。 这种安排减少了芯片上测试硬件的数量，并减少了编写复杂测试软件的需要。 可以在阴影锁存器和寻址锁存器之间插入更高级别的功能，以自动提供诸如反转的功能。
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公开(公告)号：US20090005225A1
公开(公告)日：2009-01-01
申请号：US12141369
申请日：2008-06-18
CPC分类号： G03G15/0233
摘要： A charging roll includes a shaft and an ionically conductive elastic layer formed around the shaft. The ionically conductive elastic layer is formed of a rubber composition free of any electron-conductive agent and containing 0.7 to 1.0 parts by weight of a peroxide cross-linking agent per 100 parts by weight of an ion-conductive rubber. The ion-conductive rubber is formed of at least one of an epichlorohydrin rubber and a nitrile rubber, and a percentage of a rubber component in the ionically conductive elastic layer measured by thermogravimetric analysis is 90% or more by weight.
摘要翻译： 充电辊包括轴和形成在轴周围的离子导电弹性层。 离子导电弹性层由不含任何电子传导剂的橡胶组合物形成，并且每100重量份的离子传导橡胶含有0.7-1.0重量份的过氧化物交联剂。 离子导电橡胶由表氯醇橡胶和丁腈橡胶中的至少一种形成，并且通过热重分析测定的离子导电性弹性层中的橡胶成分的百分比为90重量％以上。
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公开(公告)号：US07036391B2
公开(公告)日：2006-05-02
申请号：US10090754
申请日：2002-03-06
申请人： Kenichi Tsuchiya , Seiji Habara
发明人： Kenichi Tsuchiya , Seiji Habara
IPC分类号： B60K17/24
CPC分类号： F16C19/54 , B60K17/16 , F16C19/546 , F16C35/06 , F16C2361/61 , F16H57/021 , F16H2048/423 , Y10T74/1967 , Y10T74/19693
摘要： A protruding section facing a drive pinion shaft is integrally provided on (or provided as a separate component) a tubular spacer interposed between an inner race of a pilot bearing and an inner race of a tapered roller bearing at an inner section opposite to the drive pinion shaft. In one embodiment, a monolithic protruding section is curved so as to be convex along the overall central axial direction of the spacer, and is arch shaped in cross section. The protruding section protrudes towards the drive pinion shaft along the overall inner peripheral direction of the spacer, and the inner surface of the protruding section comes into contact with or close to the outer surface of the drive pinion shaft. Additional positions include one or a plurality of O-rings interposed between the drive pinion shaft and the inner surface of the tubular spacer.
摘要翻译： 面向驱动小齿轮轴的突出部分一体地设置在（或作为单独的部件设置）上，管状隔离件插入在先导轴承的内座圈和与驱动小齿轮相对的内部的圆锥滚子轴承的内座圈之间 轴。 在一个实施例中，整体式突出部分沿着间隔件的整个中心轴线方向是弯曲的，并且是拱形的横截面。 突出部沿着间隔件的整个内周方向向驱动小齿轮轴突出，突出部的内表面与驱动小齿轮轴的外表面接触或接近。 附加位置包括介于驱动小齿轮轴和管状间隔件的内表面之间的一个或多个O形环。
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