公开(公告)号：US20180301120A1

公开(公告)日：2018-10-18

申请号：US15488673

申请日：2017-04-17

申请人： Anupama A. Thaploo ,  Jaydeep P. Kulkarni ,  Bhushan M. Borole ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Wenyin Fu

发明人： Anupama A. Thaploo ,  Jaydeep P. Kulkarni ,  Bhushan M. Borole ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Wenyin Fu

IPC分类号： G09G5/36

摘要： In an embodiment, an apparatus includes: a repeater to receive an input signal at an input node and output an output signal at an output node; a dynamic header device coupled between the repeater and a supply voltage node; and a feedback device coupled between the output node and the dynamic header device to dynamically control the dynamic header device based at least in part on the output signal. Other embodiments are described and claimed.

公开(公告)号：US20180299921A1

公开(公告)日：2018-10-18

申请号：US15488667

申请日：2017-04-17

申请人： Iqbal R. Rajwani ,  Altug Koker ,  Bhushan M. Borole ,  Kamal Sinha ,  Abhishek R. Appu ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Wenyin Fu

发明人： Iqbal R. Rajwani ,  Altug Koker ,  Bhushan M. Borole ,  Kamal Sinha ,  Abhishek R. Appu ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Wenyin Fu

IPC分类号： G06F1/06 ,  G06F9/38 ,  G06F13/16 ,  G06F1/08 ,  G06T1/20

CPC分类号： G06F1/06 ,  G06F1/08 ,  G06F9/30141 ,  G06F9/3869 ,  G06F13/161 ,  G06F13/1673 ,  G06T1/60 ,  H03K19/096

摘要： In an embodiment, a processor includes at least one processor core and at least one graphics processor. The at least one graphics processor may include a register file having a plurality of entries, where at least a portion of the at least one graphics processor is to operate at a first operating frequency and the register file is to operate at a second operating frequency greater than the first operating frequency, to enable the at least one graphics processor to issue a plurality of write requests to the register file in a single clock cycle at the first operating frequency and receive a plurality of data elements of a plurality of read requests from the register file in the single clock cycle at the first operating frequency. Other embodiments are described and claimed.

公开(公告)号：US20180175832A1

公开(公告)日：2018-06-21

申请号：US15382076

申请日：2016-12-16

申请人： Suphachai Chai Sutanthavibul ,  Iqbal Rajwani ,  Anupama A. Thaploo ,  Surya Sasi Tallapragada ,  Daivik H. Bhatt ,  Lei Jiang ,  Stephen Kim ,  Pascal A. Meinerzhagen ,  Muhammad M. Khellah

发明人： Suphachai Chai Sutanthavibul ,  Iqbal Rajwani ,  Anupama A. Thaploo ,  Surya Sasi Tallapragada ,  Daivik H. Bhatt ,  Lei Jiang ,  Stephen Kim ,  Pascal A. Meinerzhagen ,  Muhammad M. Khellah

IPC分类号： H03K3/012 ,  H02M1/08

CPC分类号： H02M1/08 ,  H02M1/088 ,  H02M3/158 ,  H02M2001/0032 ,  H02M2001/0048 ,  H03K17/08122 ,  H03K17/6871 ,  H03K19/0013 ,  H03K19/0016 ,  H03K2017/0806 ,  H03K2217/0036 ,  Y02B70/1491

摘要： Some embodiments include apparatuses and methods using the apparatuses. One of the apparatuses includes a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information. The first, second, and third voltages have different values based on values of the digital information.