公开(公告)号：US20180299921A1

公开(公告)日：2018-10-18

申请号：US15488667

申请日：2017-04-17

申请人： Iqbal R. Rajwani ,  Altug Koker ,  Bhushan M. Borole ,  Kamal Sinha ,  Abhishek R. Appu ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Wenyin Fu

发明人： Iqbal R. Rajwani ,  Altug Koker ,  Bhushan M. Borole ,  Kamal Sinha ,  Abhishek R. Appu ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Wenyin Fu

IPC分类号： G06F1/06 ,  G06F9/38 ,  G06F13/16 ,  G06F1/08 ,  G06T1/20

CPC分类号： G06F1/06 ,  G06F1/08 ,  G06F9/30141 ,  G06F9/3869 ,  G06F13/161 ,  G06F13/1673 ,  G06T1/60 ,  H03K19/096

摘要： In an embodiment, a processor includes at least one processor core and at least one graphics processor. The at least one graphics processor may include a register file having a plurality of entries, where at least a portion of the at least one graphics processor is to operate at a first operating frequency and the register file is to operate at a second operating frequency greater than the first operating frequency, to enable the at least one graphics processor to issue a plurality of write requests to the register file in a single clock cycle at the first operating frequency and receive a plurality of data elements of a plurality of read requests from the register file in the single clock cycle at the first operating frequency. Other embodiments are described and claimed.

公开(公告)号：US20110149661A1

公开(公告)日：2011-06-23

申请号：US12642444

申请日：2009-12-18

申请人： Iqbal R. Rajwani ,  Satish K. Damaraju ,  Niranjan L. Cooray ,  Muhammad M. Khellah ,  Jaydeep P. Kulkarni

发明人： Iqbal R. Rajwani ,  Satish K. Damaraju ,  Niranjan L. Cooray ,  Muhammad M. Khellah ,  Jaydeep P. Kulkarni

IPC分类号： G11C7/00 ,  G11C8/08 ,  G11C8/18

CPC分类号： G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C11/418

摘要： In some embodiments, an apparatus comprising a memory array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns and configured to receive a clock signal having a plurality of clock cycles; a plurality of word-lines associated with the plurality of rows of the SRAM cells; and a selected word-line driver configured during an extended write operation to drive a selected one of the plurality of word-lines with a write word-line signal having an extended duration. Other embodiments may be described and claimed.

摘要翻译： 在一些实施例中，一种装置包括以多行排列并且被配置为接收具有多个时钟周期的时钟信号的静态随机存取存储器（SRAM）单元的存储器阵列; 与所述SRAM单元的所述多行相关联的多个字线; 以及在扩展写入操作期间配置的选择的字线驱动器，以用延长的持续时间的写入字线信号来驱动所述多个字线中的所选择的一个字线。 可以描述和要求保护其他实施例。