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公开(公告)号：US11909406B1
公开(公告)日：2024-02-20
申请号：US17893471
申请日：2022-08-23
Applicant: Apple Inc.
Inventor： Ahmed I Hussein , Mahdi Forghani , David M Signoff
CPC classification number: H03L7/0995 , H03L7/093
Abstract: An electronic device may include wireless circuitry having mixer circuitry configured to receive an oscillator signal from phase-locked loop circuitry. The phase-locked loop circuitry may include a digital or analog phase-locked loop having a first frequency divider, a ring oscillator, and an auxiliary phase noise cancellation loop coupled to the ring oscillator. The auxiliary phase noise cancellation loop may include at least a time-to-digital converter, a second frequency divider, an amplifier, and a bandpass filter configured to reject thermal and quantization noise associated with the time-to-digital converter. The first frequency divider may have a first division ratio, whereas the second frequency divider may have a second division ratio that is less than the first division ratio to provide faster phase noise correction.
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公开(公告)号：US20240072813A1
公开(公告)日：2024-02-29
申请号：US17893471
申请日：2022-08-23
Applicant: Apple Inc.
Inventor： Ahmed I Hussein , Mahdi Forghani , David M Signoff
CPC classification number: H03L7/0995 , H03L7/093
Abstract: An electronic device may include wireless circuitry having mixer circuitry configured to receive an oscillator signal from phase-locked loop circuitry. The phase-locked loop circuitry may include a digital or analog phase-locked loop having a first frequency divider, a ring oscillator, and an auxiliary phase noise cancellation loop coupled to the ring oscillator. The auxiliary phase noise cancellation loop may include at least a time-to-digital converter, a second frequency divider, an amplifier, and a bandpass filter configured to reject thermal and quantization noise associated with the time-to-digital converter. The first frequency divider may have a first division ratio, whereas the second frequency divider may have a second division ratio that is less than the first division ratio to provide faster phase noise correction.
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公开(公告)号：US11848680B1
公开(公告)日：2023-12-19
申请号：US17746729
申请日：2022-05-17
Applicant: Apple Inc.
Inventor： Ali Parsa , Ahmed I Hussein
Abstract: This disclosure is directed towards systems and methods that improve bandwidth shifting operations of an ADPLL without losing a lock of the ADPLL and having the benefit of being able to change the bandwidth an unlimited amount of times. Indeed, a processor may transmit amplification parameters to the ADPLL to implement a bandwidth shift. The shift may occur in response to a enable signal, such as a gear trigger control signal (gear_retime signal) or a enable signal generated to cause alignment of the shifting with a clock signal (e.g., enable signal generated by AND logic gates). These systems and methods described herein many enable multiple bandwidth changing operations to occur without compromising the complexity and footprint of the system.
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公开(公告)号：US20240146318A1
公开(公告)日：2024-05-02
申请号：US18544289
申请日：2023-12-18
Applicant: Apple Inc.
Inventor： Ali Parsa , Ahmed I Hussein
Abstract: This disclosure is directed towards systems and methods that improve bandwidth shifting operations of an ADPLL without losing a lock of the ADPLL and having the benefit of being able to change the bandwidth an unlimited amount of times. Indeed, a processor may transmit amplification parameters to the ADPLL to implement a bandwidth shift. The shift may occur in response to a enable signal, such as a gear trigger control signal (gear_retime signal) or a enable signal generated to cause alignment of the shifting with a clock signal (e.g., enable signal generated by AND logic gates). These systems and methods described herein many enable multiple bandwidth changing operations to occur without compromising the complexity and footprint of the system.
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