公开(公告)号：US20240061460A1

公开(公告)日：2024-02-22

申请号：US17820143

申请日：2022-08-16

Applicant: Apple Inc.

Inventor： Bo Sun ,  Jafar Savoj

IPC: G05F3/26 ,  H03K19/0185

CPC classification number: G05F3/262 ,  H03K19/018521

Abstract: A current mirror circuit included in a computer system that includes a mirror stage circuit and a feedback circuit is disclosed. The mirror stage circuit generates a mirror current in an output node using a reference current. The feedback circuit adjusts the value of the mirror current based on a voltage level of the output node to increase the output impedance of the current mirror circuit.

公开(公告)号：US12278719B2

公开(公告)日：2025-04-15

申请号：US17931096

申请日：2022-09-09

Applicant: Apple Inc.

Inventor： Bo Sun ,  Jafar Savoj

IPC: H04L25/03 ,  H04L7/00

Abstract: A receiver with feed-forward equalization is disclosed. A receiver includes a delay circuit configured to receive a first signal that encodes a serial data stream having a plurality of data symbols. The delay circuit includes at least one T-coil circuit and is configured to generate a plurality of delayed signals using the first signal. The receiver further includes a front-end circuit configured to generate an equalized signal using the at first signal and one or more delayed signals of the plurality of delayed signals. A sample circuit is configured to sample the equalized signal to generate a plurality of samples. A recovery circuit configured to generate a plurality of recovered data symbols using the plurality of samples.

公开(公告)号：US20240089154A1

公开(公告)日：2024-03-14

申请号：US17931096

申请日：2022-09-09

Applicant: Apple Inc.

Inventor： Bo Sun ,  Jafar Savoj

IPC: H04L25/03 ,  H04L7/00

CPC classification number: H04L25/03038 ,  H04L7/0016

Abstract: A receiver with feed-forward equalization is disclosed. A receiver includes a delay circuit configured to receive a first signal that encodes a serial data stream having a plurality of data symbols. The delay circuit includes at least one T-coil circuit and is configured to generate a plurality of delayed signals using the first signal. The receiver further includes a front-end circuit configured to generate an equalized signal using the at first signal and one or more delayed signals of the plurality of delayed signals. A sample circuit is configured to sample the equalized signal to generate a plurality of samples. A recovery circuit configured to generate a plurality of recovered data symbols using the plurality of samples.

公开(公告)号：US11586240B1

公开(公告)日：2023-02-21

申请号：US17867117

申请日：2022-07-18

Applicant: Apple Inc.

Inventor： Bo Sun ,  Brian S. Leibowitz ,  Jafar Savoj ,  Sanjeev K. Maheshwari

IPC: G06F1/08 ,  H03L7/081 ,  H03K5/01 ,  H03K5/00 ,  H03K17/56

Abstract: Embodiments relate to a circuit implementation for controlling a delay of a clock signal. The clock delay control circuit includes a sensing circuit and a phase interpolator controlled by the sensing circuit. The sensing circuit generates a first control signal that increases when a level of a supply voltage increases, and decreases when the level of the supply voltage decreases. Moreover, the sensing circuit generates a second control signal that decreases when the level of the supply voltage increases, and increases when the level of the supply voltage decreases. The phase interpolator includes multiple paths, each having a different propagation delay. The coupling between each path and the output node of the phase interpolator is controlled by the control signals generated by the sensing circuit.