公开(公告)号：US12249909B2

公开(公告)日：2025-03-11

申请号：US17895587

申请日：2022-08-25

Applicant: Apple Inc.

Inventor： Meei-Ling Chiang ,  Khaled M. Alashmouny ,  Zhi Hu

IPC: H02M1/15 ,  H02M1/44 ,  H02M3/156

Abstract: The present disclosure describes a circuit having a current source and a load circuit coupled to the current source. The current source can include a transistor electrically coupled to a voltage supply and can be configured to generate a first current with a first current rate-of-change during a time interval, where the first current can be a cancellation current. In addition, the load circuit can be configured to generate a second current with a second current rate-of-change during the same time interval, where the second current can be a load current. The second current rate-of-change can be substantially an inverse of the first current rate-of-change. A power system can include a power management unit configured to generate a power supply voltage at an output, a current source and a load circuit electrically coupled to the output, and a control circuit controls the first current rate-of-change during the time interval.

公开(公告)号：US20210167766A1

公开(公告)日：2021-06-03

申请号：US16701844

申请日：2019-12-03

Applicant: Apple Inc.

Inventor： Khaled M. Alashmouny ,  Dennis M. Fischette, JR. ,  Charles L. Wang ,  Samed Maltabas

IPC: H03K5/156 ,  G06F1/10

Abstract: A system and method for efficient on-chip monitoring of clock signals post-silicon. An electronic circuit includes a post-silicon and on-die signal monitor and a first signal generator that sends a first signal with a first signal period to the signal monitor. The signal monitor selects a first sampling signal with a first sampling period such that a ratio of the first sampling period to the first signal period is greater than one and is a non-integer. The signal monitor selects a reference voltage level for indicating when the first signal is asserted. When the first sampling period has elapsed, the signal monitor samples the first signal to generate a voltage level, and upon completing sampling, determines a duty cycle of the generated voltage levels, which indicates a duty cycle of the first signal. Using a similar approach, the signal monitor is also capable of determining skew between two signals.

公开(公告)号：US20160291625A1

公开(公告)日：2016-10-06

申请号：US14673326

申请日：2015-03-30

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Eric G. Smith ,  Erik P. Machnicki ,  Jung Wook Cho ,  Khaled M. Alashmouny ,  Kiran B. Kattel ,  Vijay M. Bettada ,  Bo Yang ,  Wenlong Wei

IPC: G05F3/02

CPC classification number: G05F3/02 ,  G06F1/324 ,  G06F1/3296

Abstract: An under voltage detection circuit and method of operating an IC including the same is disclosed. In one embodiment, an IC includes an under voltage protection circuit having first and second comparators configured to compare a supply voltage to first and second voltage thresholds, respectively, with the second voltage threshold being greater than the first. A logic circuit is coupled to receive signals from the first and second comparators. During operation in a high performance state by a corresponding functional circuit, the logic circuit is configured to cause assertion of a throttling signal responsive to an indication that the supply voltage has fallen below the first threshold. A clock signal provided to the functional circuit may be throttled responsive to the indication. If the supply voltage subsequently rises to a level above the second threshold, the throttling signal may be de-asserted.

Abstract translation: 公开了一种欠压检测电路及其运算方法。 在一个实施例中，IC包括欠压保护电路，其具有第一和第二比较器，其被配置为分别将电源电压与第一和第二电压阈值进行比较，其中第二电压阈值大于第一电压阈值。 逻辑电路被耦合以从第一和第二比较器接收信号。 在通过相应的功能电路在高性能状态下操作期间，逻辑电路被配置为响应于电源电压已经低于第一阈值的指示而导致节流信号的断言。 提供给功能电路的时钟信号可以响应于指示而被节流。 如果电源电压随后上升到高于第二阈值的水平，则节流信号可以被取消断言。

公开(公告)号：US11165416B2

公开(公告)日：2021-11-02

申请号：US16701844

申请日：2019-12-03

Applicant: Apple Inc.

Inventor： Khaled M. Alashmouny ,  Dennis M. Fischette, Jr. ,  Charles L. Wang ,  Samed Maltabas ,  Yikun Chang

IPC: H03K5/156 ,  G06F1/10

Abstract: A system and method for efficient on-chip monitoring of clock signals post-silicon. An electronic circuit includes a post-silicon and on-die signal monitor and a first signal generator that sends a first signal with a first signal period to the signal monitor. The signal monitor selects a first sampling signal with a first sampling period such that a ratio of the first sampling period to the first signal period is greater than one and is a non-integer. The signal monitor selects a reference voltage level for indicating when the first signal is asserted. When the first sampling period has elapsed, the signal monitor samples the first signal to generate a voltage level, and upon completing sampling, determines a duty cycle of the generated voltage levels, which indicates a duty cycle of the first signal. Using a similar approach, the signal monitor is also capable of determining skew between two signals.

公开(公告)号：US09658634B2

公开(公告)日：2017-05-23

申请号：US14673326

申请日：2015-03-30

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Eric G. Smith ,  Erik P. Machnicki ,  Jung Wook Cho ,  Khaled M. Alashmouny ,  Kiran B. Kattel ,  Vijay M. Bettada ,  Bo Yang ,  Wenlong Wei

IPC: G06F1/00 ,  G05F3/02 ,  G06F1/32

CPC classification number: G05F3/02 ,  G06F1/324 ,  G06F1/3296

Abstract: An under voltage detection circuit and method of operating an IC including the same is disclosed. In one embodiment, an IC includes an under voltage protection circuit having first and second comparators configured to compare a supply voltage to first and second voltage thresholds, respectively, with the second voltage threshold being greater than the first. A logic circuit is coupled to receive signals from the first and second comparators. During operation in a high performance state by a corresponding functional circuit, the logic circuit is configured to cause assertion of a throttling signal responsive to an indication that the supply voltage has fallen below the first threshold. A clock signal provided to the functional circuit may be throttled responsive to the indication. If the supply voltage subsequently rises to a level above the second threshold, the throttling signal may be de-asserted.

公开(公告)号：US11762413B2

公开(公告)日：2023-09-19

申请号：US17476307

申请日：2021-09-15

Applicant: Apple Inc.

Inventor： Suresh Balasubramanian ,  Sunil Bhosekar ,  Bruce Andrew Doyle ,  Chad O. Lackey ,  Sharath R. Srinivasan ,  Erick O. Torres ,  Khaled M. Alashmouny

IPC: G06F1/10 ,  G06F1/08

CPC classification number: G06F1/10 ,  G06F1/08

Abstract: Systems, methods, and devices are provided for calibrating and correcting a clock duty cycle. An integrated circuit may include a clock tree that provides a clock signal and a circuit that is sensitive to clock duty cycle that receives the clock signal at a lower level of the clock tree. A first duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a first target duty cycle at a higher level of the clock tree. A second duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a second target duty cycle at the lower level of the clock tree.

公开(公告)号：US20220103166A1

公开(公告)日：2022-03-31

申请号：US17476307

申请日：2021-09-15

Applicant: Apple Inc.

Inventor： Suresh Balasubramanian ,  Sunil Bhosekar ,  Bruce Andrew Doyle ,  Chad O. Lackey ,  Sharath R. Srinivasan ,  Erick O. Torres ,  Khaled M. Alashmouny

IPC: H03K5/156 ,  G11C7/22 ,  G06F1/08 ,  G06F1/10

Abstract: Systems, methods, and devices are provided for calibrating and correcting a clock duty cycle. An integrated circuit may include a clock tree that provides a clock signal and a circuit that is sensitive to clock duty cycle that receives the clock signal at a lower level of the clock tree. A first duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a first target duty cycle at a higher level of the clock tree. A second duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a second target duty cycle at the lower level of the clock tree.

公开(公告)号：US11088683B1

公开(公告)日：2021-08-10

申请号：US17031726

申请日：2020-09-24

Applicant: Apple Inc.

Inventor： Samed Maltabas ,  Khaled M. Alashmouny ,  Dennis M. Fischette, Jr.

IPC: H03K5/156

Abstract: A clock test system included in a computer system includes a clock generator circuit that generates multiple clock signals. A switch circuit selects different ones of the multiple clock signals during different time periods to generate an output clock signal. A measurement circuit measures a duty cycle of the output clock signals during the different time periods to generate multiple duty cycle measures. The measurement circuit uses the multiple duty cycle measurements to cancel a portion of duty cycle distortion in the output clock signal to determine an adjusted duty cycle value.