公开(公告)号：US11914521B1

公开(公告)日：2024-02-27

申请号：US17809822

申请日：2022-06-29

Applicant: Apple Inc.

Inventor： Wolfgang H. Klingauf ,  Muhammad Umer Amjad ,  Connie W. Cheung ,  Yueh-Ta Wu ,  Muditha Kanchana ,  John H. Kelm

IPC: G06F12/0895 ,  G06F12/0837 ,  G06F12/0873

CPC classification number: G06F12/0895 ,  G06F12/0837 ,  G06F12/0873

Abstract: A mechanism for cache quota control is disclosed. A cache memory is configured to receive access requests from a plurality of agents, wherein a given request from a given agent of the plurality of agents specifies an identification value associated with the given agent of the plurality of agents. A cache controller is coupled to the cache memory, and is configured to store indications of current allocations of the cache memory to individual ones of the plurality of agents. The cache controller is further configured to track requests to the cache memory based on identification values specified in the requests and determine whether to update allocations of the cache memory to the individual ones of the plurality of agents based on the tracked requests.

公开(公告)号：US11755489B2

公开(公告)日：2023-09-12

申请号：US17463292

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Rohit K. Gupta ,  Rohit Natarajan ,  Jurgen M. Schulz ,  Harshavardhan Kaushikkar ,  Connie W. Cheung

IPC: G06F12/0871 ,  G06F13/16 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0871 ,  G06F3/0607 ,  G06F3/067 ,  G06F3/0664 ,  G06F12/0238 ,  G06F13/1673

Abstract: A configurable interface circuit is disclosed. An integrated circuit (IC) having a particular configuration. The IC includes a memory system and a communication fabric coupled to the memory system. The IC further includes a plurality of agent circuits configured to make requests to the memory system that are in a first format that is not specific to the particular configuration of the IC. A plurality of interface circuits is coupled between corresponding ones of the plurality of agent circuits and the communication fabric. A given one of the plurality of interface circuits is configured to receive a request to the memory system in the first format and output the request in a second format that is specific to the particular configuration of the IC.

公开(公告)号：US11232033B2

公开(公告)日：2022-01-25

申请号：US16530216

申请日：2019-08-02

Applicant: Apple Inc.

Inventor： Wolfgang H. Klingauf ,  Connie W. Cheung ,  Rohit K. Gupta ,  Rohit Natarajan ,  Vanessa Cristina Heppolette ,  Varaprasad V. Lingutla ,  Muditha Kanchana

IPC: G06F12/0842 ,  G06F12/0895

Abstract: Systems, apparatuses, and methods for dynamically partitioning a memory cache among a plurality of agents are described. A system includes a plurality of agents, a communication fabric, a memory cache, and a lower-level memory. The partitioning of the memory cache for the active data streams of the agents is dynamically adjusted to reduce memory bandwidth and increase power savings across a wide range of applications. A memory cache driver monitors activations and characteristics of the data streams of the system. When a change is detected, the memory cache driver dynamically updates the memory cache allocation policy and quotas for the agents. The quotas specify how much of the memory cache each agent is allowed to use. The updates are communicated to the memory cache controller to enforce the new policy and enforce the new quotas for the various agents accessing the memory.

公开(公告)号：US20230064369A1

公开(公告)日：2023-03-02

申请号：US17463292

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Rohit K. Gupta ,  Rohit Natarajan ,  Jurgen M. Schulz ,  Harshavardhan Kaushikkar ,  Connie W. Cheung

IPC: G06F12/0871 ,  G06F12/02 ,  G06F13/16 ,  H03K19/0175

Abstract: A configurable interface circuit is disclosed. An integrated circuit (IC) having a particular configuration. The IC includes a memory system and a communication fabric coupled to the memory system. The IC further includes a plurality of agent circuits configured to make requests to the memory system that are in a first format that is not specific to the particular configuration of the IC. A plurality of interface circuits is coupled between corresponding ones of the plurality of agent circuits and the communication fabric. A given one of the plurality of interface circuits is configured to receive a request to the memory system in the first format and output the request in a second format that is specific to the particular configuration of the IC.

公开(公告)号：US20210034527A1

公开(公告)日：2021-02-04

申请号：US16530216

申请日：2019-08-02

Applicant: Apple Inc.

Inventor： Wolfgang H. Klingauf ,  Connie W. Cheung ,  Rohit K. Gupta ,  Rohit Natarajan ,  Vanessa Cristina Heppolette ,  Varaprasad V. Lingutla ,  Muditha Kanchana

IPC: G06F12/0842 ,  G06F12/0895

Abstract: Systems, apparatuses, and methods for dynamically partitioning a memory cache among a plurality of agents are described. A system includes a plurality of agents, a communication fabric, a memory cache, and a lower-level memory. The partitioning of the memory cache for the active data streams of the agents is dynamically adjusted to reduce memory bandwidth and increase power savings across a wide range of applications. A memory cache driver monitors activations and characteristics of the data streams of the system. When a change is detected, the memory cache driver dynamically updates the memory cache allocation policy and quotas for the agents. The quotas specify how much of the memory cache each agent is allowed to use. The updates are communicated to the memory cache controller to enforce the new policy and enforce the new quotas for the various agents accessing the memory.