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公开(公告)号:US20240427391A1
公开(公告)日:2024-12-26
申请号:US18438782
申请日:2024-02-12
Applicant: Apple Inc.
Inventor: Inder M. Sodhi , Achmed R. Zahir , Carmel Yamberger , Daniele Perretta , Jan Krellner , Ron Neuman , James S. Ismail , Keith Cox
Abstract: Techniques are disclosed relating to electromigration control implemented by a power management unit. In some embodiments, the power management unit itself is configured to monitor operating conditions, implement control for one or more electromigration loops, and send reduction alerts, via an inter-chip interconnect, to the processor circuitry it powers. In some embodiments, the power management unit implements both thermal and electromigration control loops. Disclosed techniques may advantageously reduce or avoid electromigration issues, potentially with reduced impact on processor performance relative to traditional techniques.
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公开(公告)号:US11934240B2
公开(公告)日:2024-03-19
申请号:US17664000
申请日:2022-05-18
Applicant: Apple Inc.
Inventor: Inder M. Sodhi , Achmed R. Zahir , Carmel Yamberger , Daniele Perretta , Jan Krellner , Ron Neuman , James S. Ismail , Keith Cox
CPC classification number: G06F1/206 , G06F1/28 , G06F11/3058
Abstract: Techniques are disclosed relating to thermal control implemented by a power management unit. In some embodiments, the power management unit itself is configured to monitor thermal conditions, implement control for one or more thermal loops, and send reduction alerts, via an inter-chip interconnect, to the processor circuitry it powers. In some embodiments, the power management unit implements both thermal and electromigration control loops. Disclosed techniques may advantageously reduce or avoid thermal issues, potentially with reduced impact on processor performance relative to traditional techniques.
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公开(公告)号:US20230376091A1
公开(公告)日:2023-11-23
申请号:US17664000
申请日:2022-05-18
Applicant: Apple Inc.
Inventor: Inder M. Sodhi , Achmed R. Zahir , Carmel Yamberger , Daniele Perretta , Jan Krellner , Ron Neuman , James S. Ismail , Keith Cox
CPC classification number: G06F1/206 , G06F1/28 , G06F11/3058
Abstract: Techniques are disclosed relating to thermal control implemented by a power management unit. In some embodiments, the power management unit itself is configured to monitor thermal conditions, implement control for one or more thermal loops, and send reduction alerts, via an inter-chip interconnect, to the processor circuitry it powers. In some embodiments, the power management unit implements both thermal and electromigration control loops. Disclosed techniques may advantageously reduce or avoid thermal issues, potentially with reduced impact on processor performance relative to traditional techniques.
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