公开(公告)号：US11169585B2

公开(公告)日：2021-11-09

申请号：US16543334

申请日：2019-08-16

Applicant: Apple Inc.

Inventor： Achmed R. Zahir ,  Inder M. Sodhi ,  John H. Kelm

IPC: G06F1/28 ,  G06F9/451 ,  G06F1/08

Abstract: Systems, methods and mechanisms for efficiently reporting sensor data of multiple processing units. In various embodiments, a computing system includes processing units and a power management unit. The processing units include multiple sensors for measuring a variety of types of sensor data. If the sensor values exceed corresponding thresholds, then a processing unit sends the sensor values to the power management unit. Logic in the power management unit stores received sensor values. When the logic determines behavior of a processing unit changes, the logic updates one or more sensor thresholds for the processing unit for changing a frequency of reporting one or more sensor values of the processing unit. The logic sends the updated one or more sensor thresholds to the processing unit. The logic updates more operating modes and operating states for the processing units based on the received sensor values.

公开(公告)号：US20200379534A1

公开(公告)日：2020-12-03

申请号：US16889232

申请日：2020-06-01

Applicant: Apple Inc.

Inventor： Achmed R. Zahir ,  Diwakar N. Tundlam ,  James S. Ismail ,  Keith Cox ,  Reza Arastoo ,  Douglas A. MacKay ,  John M. Ananny ,  Michael Eng

IPC: G06F1/28 ,  G06F1/3212 ,  H02J7/00 ,  G01R31/387 ,  G01R31/367

Abstract: Systems and methods are disclosed for allocating and distributing power management budgets for subsystems (e.g., power usage clients) of a computer system. A power budget allocation subsystem may include a plurality of feedback branches having different associated time constants. Power usage clients with slower power response times may be provided power budgets based on a feedback branch having an associated longer time constant, while power usage clients with faster power response times may be provided with power budgets based on a feedback branch having an associated shorter time constant. The power budgets may be determined in the feedback branches based on power budgeting policies weighting the power budget of each subsystem relative to total power mitigation.

公开(公告)号：US20240241561A1

公开(公告)日：2024-07-18

申请号：US18622481

申请日：2024-03-29

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  Karl D. Wulcan ,  Tal Kuzi ,  Inder M. Sodhi ,  Achmed R. Zahir ,  Ilya Granovsky ,  Nir Leshem ,  Lior Zimet

IPC: G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3293 ,  G06F1/3296

CPC classification number: G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3293 ,  G06F1/3296

Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Trigger logic circuits and rate control circuits may be implemented in combination with a power management circuit to control power provided to components of the integrated circuits. Power may be controlled based on receiving trigger signals from a power management unit. The power management circuit may implement power budgets for various components in the integrated circuits.

公开(公告)号：US20200319690A1

公开(公告)日：2020-10-08

申请号：US16373461

申请日：2019-04-02

Applicant: Apple Inc.

Inventor： Inder M. Sodhi ,  Daniel U. Becker ,  Achmed R. Zahir

IPC: G06F1/3206 ,  G06F1/3234

Abstract: An apparatus includes a processing circuit, a power processing module, and a power management circuit. The power management circuit is configured to estimate, over time, energy consumption of the processing circuit, and to sample the estimated energy consumption using a plurality of different sampling frequencies. Each of the different sampling frequencies is used to generate a respective set of power values. The power management circuit is further configured to track a particular characteristic for each set of power values, and then to provide, for each set of power values, a particular power value that corresponds to the particular characteristic to the power processing module. Based on at least one of the particular power values, the power processing module is configured to adjust an operating parameter of the processing circuit.

公开(公告)号：US20240184355A1

公开(公告)日：2024-06-06

申请号：US18438665

申请日：2024-02-12

Applicant: Apple Inc.

Inventor： Inder M. Sodhi ,  Achmed R. Zahir ,  Lior Zimet ,  Liran Fishel ,  Omri Flint ,  Ami Schwartzman

IPC: G06F1/3296 ,  G06F1/3206

CPC classification number: G06F1/3296 ,  G06F1/3206

Abstract: Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state. Techniques are further disclosed relating to managing latency tolerance events within a multi-die integrated circuit.

公开(公告)号：US20230061898A1

公开(公告)日：2023-03-02

申请号：US17676683

申请日：2022-02-21

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  Karl Daniel Wulcan ,  Tal Kuzi ,  Inder M. Sodhi ,  Achmed R. Zahir

IPC: G06F1/3293 ,  G06F1/3228

Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Specifically, a power manager circuit in an integrated circuit (e.g., a system on a chip) may modify power budgets for various components in the integrated circuit to reduce the amount of power control caused by external signaling that indicates a voltage regulator overload (e.g., a voltage droop).

公开(公告)号：US20230059725A1

公开(公告)日：2023-02-23

申请号：US17933168

申请日：2022-09-19

Applicant: Apple Inc.

Inventor： Inder M. Sodhi ,  Achmed R. Zahir ,  Lior Zimet ,  Liran Fishel ,  Omri Flint ,  Ami Schwartzman

IPC: G06F1/3296 ,  G06F1/3206

Abstract: Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state. Techniques are further disclosed relating to managing latency tolerance events within a multi-die integrated circuit.

公开(公告)号：US11467655B1

公开(公告)日：2022-10-11

申请号：US17340940

申请日：2021-06-07

Applicant: Apple Inc.

Inventor： Inder M. Sodhi ,  Achmed R. Zahir ,  Lior Zimet ,  Liran Fishel ,  Omri Flint ,  Ami Schwartzman

IPC: G06F1/00 ,  G06F1/3296 ,  G06F1/3206

Abstract: Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state. Techniques are further disclosed relating to managing latency tolerance events within a multi-die integrated circuit.

公开(公告)号：US20210048865A1

公开(公告)日：2021-02-18

申请号：US16543334

申请日：2019-08-16

Applicant: Apple Inc.

Inventor： Achmed R. Zahir ,  Inder M. Sodhi ,  John H. Kelm

IPC: G06F1/28 ,  G06F9/451 ,  G06F1/08

Abstract: Systems, methods and mechanisms for efficiently reporting sensor data of multiple processing units. In various embodiments, a computing system includes processing units and a power management unit. The processing units include multiple sensors for measuring a variety of types of sensor data. If the sensor values exceed corresponding thresholds, then a processing unit sends the sensor values to the power management unit. Logic in the power management unit stores received sensor values. When the logic determines behavior of a processing unit changes, the logic updates one or more sensor thresholds for the processing unit for changing a frequency of reporting one or more sensor values of the processing unit. The logic sends the updated one or more sensor thresholds to the processing unit. The logic updates more operating modes and operating states for the processing units based on the received sensor values.

公开(公告)号：US20240427391A1

公开(公告)日：2024-12-26

申请号：US18438782

申请日：2024-02-12

Applicant: Apple Inc.

Inventor： Inder M. Sodhi ,  Achmed R. Zahir ,  Carmel Yamberger ,  Daniele Perretta ,  Jan Krellner ,  Ron Neuman ,  James S. Ismail ,  Keith Cox

IPC: G06F1/20 ,  G06F1/28 ,  G06F11/30

Abstract: Techniques are disclosed relating to electromigration control implemented by a power management unit. In some embodiments, the power management unit itself is configured to monitor operating conditions, implement control for one or more electromigration loops, and send reduction alerts, via an inter-chip interconnect, to the processor circuitry it powers. In some embodiments, the power management unit implements both thermal and electromigration control loops. Disclosed techniques may advantageously reduce or avoid electromigration issues, potentially with reduced impact on processor performance relative to traditional techniques.