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公开(公告)号：US20250030445A1
公开(公告)日：2025-01-23
申请号：US18356956
申请日：2023-07-21
Applicant: Apple Inc.
Inventor： Tarek Khedr Abdalla Mealy , Abbas Komijani , Zhengan Yang , Reetika K Agarwal , Hongrui Wang , Zhang Jin
Abstract: This disclosure is directed to a power combiner/divider with improved operating frequency range (e.g., bandwidth) compared to other power combiners/dividers. The power combiner/divider may include an isolation circuit including a first resonant circuit and a second resonant circuit coupled to terminals (e.g., input terminals, output terminals) of the power combiner/divider. The first resonant circuit may attenuate signals having frequencies in a first frequency range below an attenuation threshold between the terminals of the power combiner/divider. The second resonant circuit may attenuate signals having frequencies in a second frequency range below an attenuation threshold between the terminals of the power combiner/divider. Accordingly, the isolation circuit may improve isolation between multiple terminals of the power combiner/divider at a wider bandwidth compared to other power combiners/dividers based attenuating cross-talk between the terminal at the first frequency range and the second frequency range.
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公开(公告)号：US20240429962A1
公开(公告)日：2024-12-26
申请号：US18214307
申请日：2023-06-26
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani , Ali Parsa
Abstract: In some source degeneration-based cascode LNAs, a cascode transistor may contribute a large portion of noise at mmWave frequencies due to lower output impedance from a bottom transistor (e.g., amplifying transistor or transconductance transistor) of the cascode. The cascode noise may negatively impact performance of the LNA. A first inductor (e.g., cascode inductor) may be coupled to the source of the cascode transistor and a second inductor (e.g., notch inductor) may be coupled to the gate of the bottom transistor such that the cascode inductor and a notch inductor inductively couple to each other, introducing a reverse-transmission zero in-band to reduce or eliminate cascode noise contribution and neutralize gate-drain capacitance of the bottom transistor with minimal area consumption.
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公开(公告)号：US11909355B2
公开(公告)日：2024-02-20
申请号：US17942850
申请日：2022-09-12
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani
CPC classification number: H03B5/12 , H03L1/00 , H04B1/40 , H03B2200/009 , H03B2200/0092 , H03B2201/038
Abstract: To prevent an undesired operating mode of voltage-controlled oscillation (VCO) circuitry from dominating a desired operating mode (e.g., an in-phase operating mode or an out-of-phase operating mode), a supply reset and ramp pulse may be provided to the VCO circuitry when switching to a new mode, such that supply voltage to the VCO circuitry is reset (e.g., set to 0 V or another reference voltage), and gradually increased or ramped up back to a steady-state voltage (e.g., used to maintain a mode) within a time duration. Additionally or alternatively, a switch control bootstrap pulse may be provided to the VCO circuitry that is bootstrapped to (e.g., applied instantaneously or concurrently with) switching the VCO circuitry to the new mode. After a time duration, the VCO circuitry may switch back to a steady-state voltage (e.g., used to maintain the new mode).
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公开(公告)号：US11894866B2
公开(公告)日：2024-02-06
申请号：US17690867
申请日：2022-03-09
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani , Xinhua Chen
IPC: H04B1/04
CPC classification number: H04B1/04 , H04B2001/0408
Abstract: Embodiments presented herein provide apparatus and techniques to reduce a direct current (DC) voltage offset between a transmitter and receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver may include a first unit gain buffer to receive a reference voltage signal from the reference voltage source. The transmitter may be communicatively coupled to the receiver via one or more connections and may include a second unit gain buffer communicatively coupled to the first unit gain buffer via one of the connections. An amplifier (e.g., an operation amplifier) of the transmitter may include multiple positive inputs coupled to the second unit gain buffer and an offset tracker. The offset tracker may compensate for a DC offset caused by at least a power supply and/or a ground bounce.
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5.发明公开公开(公告)号：US20230403013A1
公开(公告)日：2023-12-14
申请号：US17835292
申请日：2022-06-08
Applicant: Apple Inc.
Inventor： Reetika K Agarwal , Abbas Komijani , Hongrui Wang
CPC classification number: H03L7/0891 , H03L7/091 , H03L7/1976 , H03L7/185 , H03L7/099
Abstract: An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.
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Patent Agency Ranking
6.发明公开公开(公告)号：US20230378808A1
公开(公告)日：2023-11-23
申请号：US17751482
申请日：2022-05-23
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani
CPC classification number: H02J50/005 , H01F27/2804 , H02J50/12 , H01F27/027 , H01F2027/2809
Abstract: An electronic device may include wireless circuitry having a transformer adjustable between first, second, and third modes. The transformer may have first, second, third, and fourth inductors. The third inductor may be magnetically coupled to the first and second inductors with equal coupling constants. The fourth inductor may be magnetically coupled to the first and second inductors with inverse coupling constants. First and second adjustable capacitors coupled to the third and fourth inductors may receive control signals that place the transformer into a selected one of the first, second, or third modes. In the first mode the transformer exhibits a passband that overlaps first and second bands. In the second mode, the transformer passes signals in the second band while filtering interference in the first band. In the third mode, the transformer passes signals in the first band while filtering interference in the second band.
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公开(公告)号：US20230090770A1
公开(公告)日：2023-03-23
申请号：US17748904
申请日：2022-05-19
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani
Abstract: To prevent an undesired operating mode of voltage-controlled oscillation (VCO) circuitry from dominating a desired operating mode (e.g., an in-phase operating mode or an out-of-phase operating mode), a supply reset and ramp pulse may be provided to the VCO circuitry when switching to a new mode, such that supply voltage to the VCO circuitry is reset (e.g., set to 0 V or another reference voltage), and gradually increased or ramped up back to a steady-state voltage (e.g., used to maintain a mode) within a time duration. Additionally or alternatively, a switch control bootstrap pulse may be provided to the VCO circuitry that is bootstrapped to (e.g., applied instantaneously or concurrently with) switching the VCO circuitry to the new mode. After a time duration, the VCO circuitry may switch back to a steady-state voltage (e.g., used to maintain the new mode).
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公开(公告)号：US20240348254A1
公开(公告)日：2024-10-17
申请号：US18135343
申请日：2023-04-17
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani , Hideya Oshima , Reetika K Agarwal
CPC classification number: H03L7/0893 , H02M3/07
Abstract: In a charge pump-based PLL circuit, charge pump output current variation may cause phase instability at an output of a VCO. The output current variation may be caused by low-frequency disturbances (e.g., tuning voltage (Vtune) drift with channel length modulation effect), disturbance in a gate bias voltage of a transistor, or a VDD transient. Such a low-frequency disturbance may occur during initial lock, which may affect phase settling time, or after lock, which may result in phase instability. A replica charge pump and a current filtering and compensation circuit may be implemented at the output of a main charge pump to provide error current compensation to suppress channel length modulation effect, improve phase stability, and reduce phase noise.
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公开(公告)号：US12074568B2
公开(公告)日：2024-08-27
申请号：US17941767
申请日：2022-09-09
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani
CPC classification number: H03B5/1228 , H03B5/1243 , H03L7/0891 , H03L7/093
Abstract: Voltage-controlled oscillation circuitry includes multiple cores and multiple mode or gain boosters coupled between the multiple cores. To prevent an undesired operating mode of the voltage-controlled oscillation circuitry from dominating a desired operating mode (e.g., an in-phase operating mode or an out-of-phase operating mode), the mode boosters may increase a desired gain of the desired operating mode and decrease an undesired gain of the undesired operating modes. In particular, mode boosters coupled to terminals of the cores that are associated with the desired operating mode may be enabled, while mode boosters coupled to terminals of the cores that are associated with the undesired operating mode may be disabled.
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公开(公告)号：US11817823B2
公开(公告)日：2023-11-14
申请号：US17748904
申请日：2022-05-19
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani
CPC classification number: H03B5/12 , H03L1/00 , H04B1/40 , H03B2200/009 , H03B2200/0092 , H03B2201/038
Abstract: To prevent an undesired operating mode of voltage-controlled oscillation (VCO) circuitry from dominating a desired operating mode (e.g., an in-phase operating mode or an out-of-phase operating mode), a supply reset and ramp pulse may be provided to the VCO circuitry when switching to a new mode, such that supply voltage to the VCO circuitry is reset (e.g., set to 0 V or another reference voltage), and gradually increased or ramped up back to a steady-state voltage (e.g., used to maintain a mode) within a time duration. Additionally or alternatively, a switch control bootstrap pulse may be provided to the VCO circuitry that is bootstrapped to (e.g., applied instantaneously or concurrently with) switching the VCO circuitry to the new mode. After a time duration, the VCO circuitry may switch back to a steady-state voltage (e.g., used to maintain the new mode).
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