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公开(公告)号：US20240357734A1
公开(公告)日：2024-10-24
申请号：US18474880
申请日：2023-09-26
Applicant: Apple Inc.
Inventor： Behzad Biglarbegian , Hongrui Wang , Abbas Komijani , Reetika K Agarwal
CPC classification number: H05K1/0243 , H01P3/08 , H05K2201/10015 , H05K2201/1003 , H05K2201/10075
Abstract: An electronic device may include a transceiver with a substrate and an inductor on the substrate. A ring of ground traces may surround the inductor. Circuit components may be patterned onto the substrate overlapping the inductor, a region of the substrate surrounded by the inductor, and/or a region of the substrate between the inductor and the ring. The components may be arranged in trees with feed lines extending radially outward from a central axis. The components in each tree may be separated from the capacitors in other trees by gaps, preventing eddy currents on the trees. The components may be used to form bypass capacitors for power supply lines, a low-dropout regulator load, part of the loop filter of a phase-locked loop, or other portions of the transceiver. The components may thereby be used to convey signals while also meeting fill factor requirements associated with fabrication of the substrate.
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公开(公告)号：US20240348254A1
公开(公告)日：2024-10-17
申请号：US18135343
申请日：2023-04-17
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani , Hideya Oshima , Reetika K Agarwal
CPC classification number: H03L7/0893 , H02M3/07
Abstract: In a charge pump-based PLL circuit, charge pump output current variation may cause phase instability at an output of a VCO. The output current variation may be caused by low-frequency disturbances (e.g., tuning voltage (Vtune) drift with channel length modulation effect), disturbance in a gate bias voltage of a transistor, or a VDD transient. Such a low-frequency disturbance may occur during initial lock, which may affect phase settling time, or after lock, which may result in phase instability. A replica charge pump and a current filtering and compensation circuit may be implemented at the output of a main charge pump to provide error current compensation to suppress channel length modulation effect, improve phase stability, and reduce phase noise.
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公开(公告)号：US20240357733A1
公开(公告)日：2024-10-24
申请号：US18303486
申请日：2023-04-19
Applicant: Apple Inc.
Inventor： Behzad Biglarbegian , Hongrui Wang , Abbas Komijani , Reetika K Agarwal
CPC classification number: H05K1/0243 , H01P3/08 , H05K2201/10015 , H05K2201/1003 , H05K2201/10075
Abstract: An electronic device may include a transceiver with a substrate and an inductor on the substrate. A ring of ground traces may surround the inductor. Circuit components may be patterned onto the substrate overlapping the inductor, a region of the substrate surrounded by the inductor, and/or a region of the substrate between the inductor and the ring. The components may be arranged in trees with feed lines extending radially outward from a central axis. The components in each tree may be separated from the capacitors in other trees by gaps, preventing eddy currents on the trees. The components may be used to form bypass capacitors for power supply lines, a low-dropout regulator load, part of the loop filter of a phase-locked loop, or other portions of the transceiver. The components may thereby be used to convey signals while also meeting fill factor requirements associated with fabrication of the substrate.
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Patent Agency Ranking
4.发明授权公开(公告)号：US11955979B2
公开(公告)日：2024-04-09
申请号：US17835292
申请日：2022-06-08
Applicant: Apple Inc.
Inventor： Reetika K Agarwal , Abbas Komijani , Hongrui Wang
CPC classification number: H03L7/0891 , H03C3/0941 , H03L7/091 , H03L7/099 , H03L7/185 , H03L7/1976 , H04L7/033
Abstract: An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.
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公开(公告)号：US20250030445A1
公开(公告)日：2025-01-23
申请号：US18356956
申请日：2023-07-21
Applicant: Apple Inc.
Inventor： Tarek Khedr Abdalla Mealy , Abbas Komijani , Zhengan Yang , Reetika K Agarwal , Hongrui Wang , Zhang Jin
Abstract: This disclosure is directed to a power combiner/divider with improved operating frequency range (e.g., bandwidth) compared to other power combiners/dividers. The power combiner/divider may include an isolation circuit including a first resonant circuit and a second resonant circuit coupled to terminals (e.g., input terminals, output terminals) of the power combiner/divider. The first resonant circuit may attenuate signals having frequencies in a first frequency range below an attenuation threshold between the terminals of the power combiner/divider. The second resonant circuit may attenuate signals having frequencies in a second frequency range below an attenuation threshold between the terminals of the power combiner/divider. Accordingly, the isolation circuit may improve isolation between multiple terminals of the power combiner/divider at a wider bandwidth compared to other power combiners/dividers based attenuating cross-talk between the terminal at the first frequency range and the second frequency range.
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6.发明公开公开(公告)号：US20230403013A1
公开(公告)日：2023-12-14
申请号：US17835292
申请日：2022-06-08
Applicant: Apple Inc.
Inventor： Reetika K Agarwal , Abbas Komijani , Hongrui Wang
CPC classification number: H03L7/0891 , H03L7/091 , H03L7/1976 , H03L7/185 , H03L7/099
Abstract: An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.
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公开(公告)号：US12199621B2
公开(公告)日：2025-01-14
申请号：US18135343
申请日：2023-04-17
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani , Hideya Oshima , Reetika K Agarwal
Abstract: In a charge pump-based PLL circuit, charge pump output current variation may cause phase instability at an output of a VCO. The output current variation may be caused by low-frequency disturbances (e.g., tuning voltage (Vtune) drift with channel length modulation effect), disturbance in a gate bias voltage of a transistor, or a VDD transient. Such a low-frequency disturbance may occur during initial lock, which may affect phase settling time, or after lock, which may result in phase instability. A replica charge pump and a current filtering and compensation circuit may be implemented at the output of a main charge pump to provide error current compensation to suppress channel length modulation effect, improve phase stability, and reduce phase noise.
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公开(公告)号：US20240372511A1
公开(公告)日：2024-11-07
申请号：US18142540
申请日：2023-05-02
Applicant: Apple Inc.
Inventor： Hongrui Wang , Reetika K Agarwal , James Mawdsley , Abbas Komijani
Abstract: This disclosure is directed to an amplifier (e.g., a variable gain amplifier (VGA)) with improved linearity compared to other amplifiers. The amplifier may include degeneration inductors and a tunable degeneration resistor to generate amplified signals. The degeneration inductors and the tunable degeneration resistor may form a resonant circuit to improve linearity of the amplified signal at a desired frequency by reducing direct current (DC) components and harmonic components of the amplified signal having the desired frequency. Moreover, the amplifier may also generate the amplified signals with improved linearity at back-off output powers based on using the tunable degeneration resistor and the degeneration inductors. As such, the amplifier may include the degeneration inductors and the tunable degeneration resistor to generate the amplified signals having an output power across a range of output powers, such as a peak output power and one or multiple back-off output powers, with improved linearity.
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