公开(公告)号：US09607125B1

公开(公告)日：2017-03-28

申请号：US14732971

申请日：2015-06-08

Applicant: Apple Inc.

Inventor： Antonietta Oliva ,  Karthik Rajagopal ,  Manoj Gopalan ,  Mini Nanua ,  Sambasivan Narayan

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/76

Abstract: Embodiments of an electromigration (EM) check scheme to reduce a pessimism on current density limits by checking wire context. This methodology, in an embodiment, includes applying existing electronic design automation (EDA) flows and tools to identify potentially-failing wires based on a worst-case EM check using conservative foundry current density limits. A more accurate, context-specific check can be performed on the potentially-failing wires to eliminate one or more of the potentially-failing wires if those wires do not experience worst-case conditions and meet current density limits based on an actual context of those wires. A designer can correct remaining wires which are not eliminated by the context-specific check.