公开(公告)号：US12170478B2

公开(公告)日：2024-12-17

申请号：US17820168

申请日：2022-08-16

Applicant: Apple Inc.

Inventor： Alexander B. Uan-Zo-li ,  Shuai Jiang ,  Jamie L Langlinais ,  Per H. Hammarlund ,  Hans L Yeager ,  Victor Zyuban ,  Sung J. Kim ,  Wei Xu ,  Rohan U. Mandrekar ,  Sambasivan Narayan ,  Mohamed H. Abu-Rahma ,  Jaroslav Raszka ,  Robert O. Bruckner

IPC: H02M1/00

Abstract: A power delivery sub-system included in a computer system employs a primary voltage regulator circuit that generates a primary supply voltage on a primary power supply node. The power delivery sub-system also includes multiple bypass voltage regulator circuits that source corresponding bypass currents to a local power supply nodes in an integrated circuit. The integrated circuit includes multiple circuit blocks coupled to corresponding ones of the local power supply nodes, and multiple local voltage regulator circuits coupled to the primary power supply node. When a voltage level of a given local power supply node drops below a threshold value, a corresponding local voltage regulator circuit sources a supply current to the given local power supply node.

公开(公告)号：US20230299068A1

公开(公告)日：2023-09-21

申请号：US17655678

申请日：2022-03-21

Applicant: Apple Inc.

Inventor： Sambasivan Narayan ,  Praveen Raghavan

IPC: H01L27/02 ,  H01L27/11 ,  H01L23/522 ,  G11C5/06

CPC classification number: H01L27/0207 ,  H01L27/1116 ,  H01L27/1104 ,  H01L27/1108 ,  H01L23/5226 ,  G11C5/063

Abstract: A cell layout that may be implemented in FinFET devices or other FET devices is disclosed. The cell layout includes a control signal route that passes from a first device into backside layers and then underneath a second device. The control signal route then routes back to topside metal layers through inactive transistors that are implemented as via structures on the other side of the second device. Connection to the gate of the second device may then be completed through the topside metal layers. The disclosed control signal route provides a low resistance path that reduces RC delay in the devices in the cell layout.

公开(公告)号：US20250015701A1

公开(公告)日：2025-01-09

申请号：US18893579

申请日：2024-09-23

Applicant: Apple Inc.

Inventor： Alexander B. Uan-Zo-li ,  Shuai Jiang ,  Jamie L. Langlinais ,  Per H. Hammarlund ,  Hans L. Yeager ,  Victor Zyuban ,  Sung J. Kim ,  Wei Xu ,  Rohan U. Mandrekar ,  Sambasivan Narayan ,  Mohamed H. Abu-Rahma ,  Jaroslav Raszka ,  Robert O. Bruckner

IPC: H02M1/00

Abstract: A power delivery sub-system included in a computer system employs a primary voltage regulator circuit that generates a primary supply voltage on a primary power supply node. The power delivery sub-system also includes multiple bypass voltage regulator circuits that source corresponding bypass currents to a local power supply nodes in an integrated circuit. The integrated circuit includes multiple circuit blocks coupled to corresponding ones of the local power supply nodes, and multiple local voltage regulator circuits coupled to the primary power supply node. When a voltage level of a given local power supply node drops below a threshold value, a corresponding local voltage regulator circuit sources a supply current to the given local power supply node.

公开(公告)号：US20240063715A1

公开(公告)日：2024-02-22

申请号：US17820168

申请日：2022-08-16

Applicant: Apple Inc.

Inventor： Alexander B. Uan-Zo-li ,  Shuai Jiang ,  Jamie L. Langlinais ,  Per H. Hammarlund ,  Hans L. Yeager ,  Victor Zyuban ,  Sung J. Kim ,  Wei Xu ,  Rohan U. Mandrekar ,  Sambasivan Narayan ,  Mohamed H. Abu-Rahma ,  Jaroslav Raszka ,  Robert O. Bruckner

IPC: H02M3/07 ,  H02M1/00

CPC classification number: H02M3/07 ,  H02M1/0067

Abstract: A power delivery sub-system included in a computer system employs a primary voltage regulator circuit that generates a primary supply voltage on a primary power supply node. The power delivery sub-system also includes multiple bypass voltage regulator circuits that source corresponding bypass currents to a local power supply nodes in an integrated circuit. The integrated circuit includes multiple circuit blocks coupled to corresponding ones of the local power supply nodes, and multiple local voltage regulator circuits coupled to the primary power supply node. When a voltage level of a given local power supply node drops below a threshold value, a corresponding local voltage regulator circuit sources a supply current to the given local power supply node.

公开(公告)号：US20230299001A1

公开(公告)日：2023-09-21

申请号：US17655716

申请日：2022-03-21

Applicant: Apple Inc.

Inventor： Sambasivan Narayan ,  Praveen Raghavan

IPC: H01L23/528 ,  H01L29/417

CPC classification number: H01L23/5286 ,  H01L29/4175

Abstract: A standard cell layout that may be implemented in FinFET devices or nanosheet FET devices is disclosed. The standard cell layout includes power supply connections from both a topside metal layer and a backside metal layer. A device in the standard cell may be connected to both the topside metal layer and the backside metal layer. Source/drain regions of the device may be connected the metal layers using via contacts within the standard cell layout. Connections to power supply rails from the topside metal layer and the backside metal layer may also be included in the standard cell layout. The rails may be connected to a power supply such that the power supply provides power to the device through both the topside and backside metal layers.

公开(公告)号：US10396778B1

公开(公告)日：2019-08-27

申请号：US15609687

申请日：2017-05-31

Applicant: Apple Inc.

Inventor： Sambasivan Narayan ,  Suparn Vats ,  Sangeetha Mani

IPC: H03K19/003 ,  H03K19/00 ,  H03K19/20 ,  G11C5/14 ,  H03K19/23 ,  G11C11/413 ,  G06F17/50 ,  H03K17/687

Abstract: A device is disclosed that includes a circuit block coupled to a local power node, and a power gating circuit coupled between the local power node and a global power supply. In one embodiment, the power gating circuit includes a first plurality of first switching devices with a first threshold voltage, and a second plurality of second switching devices with a second threshold voltage that is different from the first voltage threshold. The power gating circuit may isolate the local power node from the global power supply based on an isolation signal.

公开(公告)号：US09607125B1

公开(公告)日：2017-03-28

申请号：US14732971

申请日：2015-06-08

Applicant: Apple Inc.

Inventor： Antonietta Oliva ,  Karthik Rajagopal ,  Manoj Gopalan ,  Mini Nanua ,  Sambasivan Narayan

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/76

Abstract: Embodiments of an electromigration (EM) check scheme to reduce a pessimism on current density limits by checking wire context. This methodology, in an embodiment, includes applying existing electronic design automation (EDA) flows and tools to identify potentially-failing wires based on a worst-case EM check using conservative foundry current density limits. A more accurate, context-specific check can be performed on the potentially-failing wires to eliminate one or more of the potentially-failing wires if those wires do not experience worst-case conditions and meet current density limits based on an actual context of those wires. A designer can correct remaining wires which are not eliminated by the context-specific check.