公开(公告)号：US20230388100A1

公开(公告)日：2023-11-30

申请号：US18152492

申请日：2023-01-10

Applicant: Apple Inc.

Inventor： Hairong Yu ,  Boon-Aik Ang ,  Yu Chen ,  Litesh Sajnani ,  Samed Maltabas ,  Shaobo Liu ,  Gregory N. Santos ,  Richard Y. Su ,  Meei-Ling Chiang ,  Pyoungwon Park ,  Dennis M. Fischette, JR.

IPC: H04L7/033 ,  H03L7/093

CPC classification number: H04L7/0337 ,  H04L7/0331 ,  H03L7/093

Abstract: A clock generator circuit may include a multiplex circuit and a phase-locked loop circuit. The multiplex circuit may generate a reference clock signal for the phase-locked loop circuit by selecting one of different clock signals. In response to a switch of the reference clock signal from one clock signal to another, the phase-locked loop circuit may disable phase-locking and enter into a frequency acquisition mode during which the frequency of the phase-locked loop circuit's output clock signal is adjusted based on the frequency of the newly selected reference clock signal. After a period of time has elapsed, the phase-locked loop circuit returns to phase-locking operation.

公开(公告)号：US12160497B2

公开(公告)日：2024-12-03

申请号：US18152492

申请日：2023-01-10

Applicant: Apple Inc.

Inventor： Hairong Yu ,  Boon-Aik Ang ,  Yu Chen ,  Litesh Sajnani ,  Samed Maltabas ,  Shaobo Liu ,  Gregory N. Santos ,  Richard Y. Su ,  Meei-Ling Chiang ,  Pyoungwon Park ,  Dennis M Fischette, Jr.

IPC: H04L7/00 ,  H03L7/093 ,  H04L7/033

Abstract: A clock generator circuit may include a multiplex circuit and a phase-locked loop circuit. The multiplex circuit may generate a reference clock signal for the phase-locked loop circuit by selecting one of different clock signals. In response to a switch of the reference clock signal from one clock signal to another, the phase-locked loop circuit may disable phase-locking and enter into a frequency acquisition mode during which the frequency of the phase-locked loop circuit's output clock signal is adjusted based on the frequency of the newly selected reference clock signal. After a period of time has elapsed, the phase-locked loop circuit returns to phase-locking operation.