公开(公告)号：US20230388100A1

公开(公告)日：2023-11-30

申请号：US18152492

申请日：2023-01-10

Applicant: Apple Inc.

Inventor： Hairong Yu ,  Boon-Aik Ang ,  Yu Chen ,  Litesh Sajnani ,  Samed Maltabas ,  Shaobo Liu ,  Gregory N. Santos ,  Richard Y. Su ,  Meei-Ling Chiang ,  Pyoungwon Park ,  Dennis M. Fischette, JR.

IPC: H04L7/033 ,  H03L7/093

CPC classification number: H04L7/0337 ,  H04L7/0331 ,  H03L7/093

Abstract: A clock generator circuit may include a multiplex circuit and a phase-locked loop circuit. The multiplex circuit may generate a reference clock signal for the phase-locked loop circuit by selecting one of different clock signals. In response to a switch of the reference clock signal from one clock signal to another, the phase-locked loop circuit may disable phase-locking and enter into a frequency acquisition mode during which the frequency of the phase-locked loop circuit's output clock signal is adjusted based on the frequency of the newly selected reference clock signal. After a period of time has elapsed, the phase-locked loop circuit returns to phase-locking operation.

公开(公告)号：US12249909B2

公开(公告)日：2025-03-11

申请号：US17895587

申请日：2022-08-25

Applicant: Apple Inc.

Inventor： Meei-Ling Chiang ,  Khaled M. Alashmouny ,  Zhi Hu

IPC: H02M1/15 ,  H02M1/44 ,  H02M3/156

Abstract: The present disclosure describes a circuit having a current source and a load circuit coupled to the current source. The current source can include a transistor electrically coupled to a voltage supply and can be configured to generate a first current with a first current rate-of-change during a time interval, where the first current can be a cancellation current. In addition, the load circuit can be configured to generate a second current with a second current rate-of-change during the same time interval, where the second current can be a load current. The second current rate-of-change can be substantially an inverse of the first current rate-of-change. A power system can include a power management unit configured to generate a power supply voltage at an output, a current source and a load circuit electrically coupled to the output, and a control circuit controls the first current rate-of-change during the time interval.

公开(公告)号：US11256283B2

公开(公告)日：2022-02-22

申请号：US16736776

申请日：2020-01-07

Applicant: Apple Inc.

Inventor： Meei-Ling Chiang ,  Dabin Zhang ,  Dennis M. Fischette, Jr. ,  Shaobo Liu ,  Yu Chen ,  Samed Maltabas

IPC: H03K23/00 ,  G06F1/04 ,  H03K7/06 ,  H03K23/58

Abstract: Systems, apparatuses, and methods for implementing a hybrid asynchronous gray counter with a non-gray zone detector are described. A circuit includes an asynchronous gray counter coupled to control logic. The control logic programs the asynchronous gray counter to operate in different modes to perform various functions associated with a high-performance phase-locked loop (PLL). In a first mode, the asynchronous gray counter serves as a frequency detector to count oscillator cycles within a reference clock cycle. In a second mode, the asynchronous gray counter serves as a coarse phase detector to detect a phase error between a feedback clock and a reference clock. In a third mode, the asynchronous gray counter serves as a multi-modulus divider to divide an oscillator clock down to create a feedback clock. Using a single asynchronous gray counter for three separate functions reduces power consumption and area utilization.

公开(公告)号：US20210208621A1

公开(公告)日：2021-07-08

申请号：US16736776

申请日：2020-01-07

Applicant: Apple Inc.

Inventor： Meei-Ling Chiang ,  Dabin Zhang ,  Dennis M. Fischette, JR. ,  Shaobo Liu ,  Yu Chen ,  Samed Maltabas

IPC: G06F1/04

Abstract: Systems, apparatuses, and methods for implementing a hybrid asynchronous gray counter with a non-gray zone detector are described. A circuit includes an asynchronous gray counter coupled to control logic. The control logic programs the asynchronous gray counter to operate in different modes to perform various functions associated with a high-performance phase-locked loop (PLL). In a first mode, the asynchronous gray counter serves as a frequency detector to count oscillator cycles within a reference clock cycle. In a second mode, the asynchronous gray counter serves as a coarse phase detector to detect a phase error between a feedback clock and a reference clock. In a third mode, the asynchronous gray counter serves as a multi-modulus divider to divide an oscillator clock down to create a feedback clock. Using a single asynchronous gray counter for three separate functions reduces power consumption and area utilization.

公开(公告)号：US12160497B2

公开(公告)日：2024-12-03

申请号：US18152492

申请日：2023-01-10

Applicant: Apple Inc.

Inventor： Hairong Yu ,  Boon-Aik Ang ,  Yu Chen ,  Litesh Sajnani ,  Samed Maltabas ,  Shaobo Liu ,  Gregory N. Santos ,  Richard Y. Su ,  Meei-Ling Chiang ,  Pyoungwon Park ,  Dennis M Fischette, Jr.

IPC: H04L7/00 ,  H03L7/093 ,  H04L7/033

Abstract: A clock generator circuit may include a multiplex circuit and a phase-locked loop circuit. The multiplex circuit may generate a reference clock signal for the phase-locked loop circuit by selecting one of different clock signals. In response to a switch of the reference clock signal from one clock signal to another, the phase-locked loop circuit may disable phase-locking and enter into a frequency acquisition mode during which the frequency of the phase-locked loop circuit's output clock signal is adjusted based on the frequency of the newly selected reference clock signal. After a period of time has elapsed, the phase-locked loop circuit returns to phase-locking operation.

公开(公告)号：US09979405B1

公开(公告)日：2018-05-22

申请号：US15429481

申请日：2017-02-10

Applicant: Apple Inc.

Inventor： Wei Deng ,  Dennis M. Fischette, Jr. ,  Meei-Ling Chiang ,  Samed Maltabas

IPC: H03L7/06 ,  H03L7/095 ,  H03L7/091 ,  H03L7/099

CPC classification number: H03L7/081 ,  H03L7/085 ,  H03L7/1976

Abstract: A digital PLL is disclosed. In one embodiment, the digital PLL includes a TDC coupled to receive a reference clock signal and feedback signal. The TDC includes a chain of serially-coupled delay elements. An oscillator in the PLL is configured to generate a periodic output signal. A divider is coupled to receive the periodic output signal and generate the feedback signal provided to the TDC. The digital PLL also includes a control circuit. During a phase-locking procedure, each of the serially-coupled delay elements is enabled for fast phase capture. However, once phase-lock has been detected by observing TDC output code, the control circuit is adaptively configured to disable all but a subset of the delay elements for saving power.