公开(公告)号：US20190026501A1

公开(公告)日：2019-01-24

申请号：US16128396

申请日：2018-09-11

Applicant: Apple Inc.

Inventor： Pierre-Olivier J. Martel ,  Jeffrey R. Wilcox ,  Ian P. Shaeffer ,  Andrew D. Myrick ,  Robert W. Hill ,  Tristan F. Schaap

IPC: G06F21/76 ,  G06F21/32

Abstract: Techniques are disclosed in which a secure circuit controls a gating circuit to enable or disable other circuitry of a device (e.g., one or more input sensors). For example, the gating circuit may be a power gating circuit and the secure circuit may be configured to disable power to an input sensor in certain situations. As another example, the gating circuit may be a clock gating circuit and the secure circuit may be configured to disable the clock to an input sensor. As yet another example, the gating circuit may be configured to gate a control bus and the secure circuit may be configured to disable control signals to an input sensor. In some embodiments, hardware resources included in or controlled by the secure circuit are not accessible by other elements of the device, other than by sending requests to a predetermined set of memory locations (e.g., a secure mailbox).

公开(公告)号：US20180349649A1

公开(公告)日：2018-12-06

申请号：US15720736

申请日：2017-09-29

Applicant: Apple Inc.

Inventor： Pierre-Olivier J. Martel ,  Jeffrey R. Wilcox ,  Ian P. Shaeffer ,  Andrew D. Myrick ,  Robert W. Hill ,  Tristan F. Schaap

IPC: G06F21/76 ,  G06F21/74 ,  G06F21/81

CPC classification number: G06F21/71 ,  G06F1/3237 ,  G06F1/3287 ,  G06F21/57 ,  G06F21/62 ,  G06F2221/2111 ,  G06F2221/2141 ,  G06F2221/2151 ,  H01L23/57 ,  H04L63/0861 ,  H04L63/107 ,  H04L63/108

Abstract: Techniques are disclosed in which a secure circuit controls a gating circuit to enable or disable other circuity of a device (e.g., one or more input sensors). For example, the gating circuit may be a power gating circuit and the secure circuit may be configured to disable power to an input sensor in certain situations. As another example, the gating circuit may be a clock gating circuit and the secure circuit may be configured to disable the clock to an input sensor. As yet another example, the gating circuit may be configured to gate a control bus and the secure circuit may be configured to disable control signals to an input sensor. In some embodiments, hardware resources included in or controlled by the secure circuit are not accessible by other elements of the device, other than by sending requests to a predetermined set of memory locations (e.g., a secure mailbox).

公开(公告)号：US10747908B2

公开(公告)日：2020-08-18

申请号：US16128396

申请日：2018-09-11

Applicant: Apple Inc.

Inventor： Pierre-Olivier J. Martel ,  Jeffrey R. Wilcox ,  Ian P. Shaeffer ,  Andrew D. Myrick ,  Robert W. Hill ,  Tristan F. Schaap

IPC: G06F21/32 ,  G06F21/76 ,  G06F21/81

Abstract: Techniques are disclosed in which a secure circuit controls a gating circuit to enable or disable other circuitry of a device (e.g., one or more input sensors). For example, the gating circuit may be a power gating circuit and the secure circuit may be configured to disable power to an input sensor in certain situations. As another example, the gating circuit may be a clock gating circuit and the secure circuit may be configured to disable the clock to an input sensor. As yet another example, the gating circuit may be configured to gate a control bus and the secure circuit may be configured to disable control signals to an input sensor. In some embodiments, hardware resources included in or controlled by the secure circuit are not accessible by other elements of the device, other than by sending requests to a predetermined set of memory locations (e.g., a secure mailbox).

公开(公告)号：US11176280B2

公开(公告)日：2021-11-16

申请号：US15720736

申请日：2017-09-29

Applicant: Apple Inc.

Inventor： Pierre-Olivier J. Martel ,  Jeffrey R. Wilcox ,  Ian P. Shaeffer ,  Andrew D. Myrick ,  Robert W. Hill ,  Tristan F. Schaap

IPC: H04L29/06 ,  G06F21/76 ,  G06F21/71 ,  G06F21/57 ,  G06F21/74 ,  G06F21/81 ,  G06F1/3237 ,  G06F21/62 ,  G06F1/3287

Abstract: Techniques are disclosed in which a secure circuit controls a gating circuit to enable or disable other circuity of a device (e.g., one or more input sensors). For example, the gating circuit may be a power gating circuit and the secure circuit may be configured to disable power to an input sensor in certain situations. As another example, the gating circuit may be a clock gating circuit and the secure circuit may be configured to disable the clock to an input sensor. As yet another example, the gating circuit may be configured to gate a control bus and the secure circuit may be configured to disable control signals to an input sensor. In some embodiments, hardware resources included in or controlled by the secure circuit are not accessible by other elements of the device, other than by sending requests to a predetermined set of memory locations (e.g., a secure mailbox).