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公开(公告)号：US12055984B2
公开(公告)日：2024-08-06
申请号：US17444269
申请日：2021-08-02
Applicant: Apple Inc.
Inventor： Michael E. Leclerc , Brett W. Degner , Ian P. Shaeffer
CPC classification number: G06F1/1684 , G06F1/181 , G06F1/203
Abstract: A computing device can include an enclosure that defines an internal volume and an external surface. An input component can be positioned at the external surface. A processing unit and a memory can be communicatively coupled and disposed within the internal volume. A singular input/output port can be positioned at an orifice defined by the enclosure. The singular input/output port can be communicatively coupled to the processing unit and the memory. The singular input/output port can be configured to receive data and power and configured to output data from the processing unit. The computing device can include an air-moving apparatus to move air along an airflow pathway. The enclosure can include a thermally conductive base.
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公开(公告)号：US11741041B2
公开(公告)日：2023-08-29
申请号：US17668512
申请日：2022-02-10
Applicant: Apple Inc.
Inventor： Ian P. Shaeffer , Eric C. Gaertner , John T Orchard , Michael W. Murphy , Ronald P. Songco , Corey N. Axelowitz , Brett W. Degner
CPC classification number: G06F13/4282 , H01R12/737 , H01R13/6683 , G06F2213/0026 , H01R2201/06
Abstract: A computer includes a processor, a PCIe-compatible interface bus that includes a root that is connected to the processor, and a routing complex that is connected to the root and is controlled by the processor. The computer also includes a first interface slot that is connectable to the root by the switches, a second interface slot that is connectable to the root by the switches, and an extended interface slot that is connectable to the root by the switches. The switches are configured based on properties of a first peripheral device to define a first switching configuration when the first peripheral device is connected only to the first interface slot and to define a second switching configuration when the first peripheral device is connected to both of the first interface slot and the extended interface slot.
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公开(公告)号：US11176280B2
公开(公告)日：2021-11-16
申请号：US15720736
申请日：2017-09-29
Applicant: Apple Inc.
Inventor： Pierre-Olivier J. Martel , Jeffrey R. Wilcox , Ian P. Shaeffer , Andrew D. Myrick , Robert W. Hill , Tristan F. Schaap
IPC: H04L29/06 , G06F21/76 , G06F21/71 , G06F21/57 , G06F21/74 , G06F21/81 , G06F1/3237 , G06F21/62 , G06F1/3287
Abstract: Techniques are disclosed in which a secure circuit controls a gating circuit to enable or disable other circuity of a device (e.g., one or more input sensors). For example, the gating circuit may be a power gating circuit and the secure circuit may be configured to disable power to an input sensor in certain situations. As another example, the gating circuit may be a clock gating circuit and the secure circuit may be configured to disable the clock to an input sensor. As yet another example, the gating circuit may be configured to gate a control bus and the secure circuit may be configured to disable control signals to an input sensor. In some embodiments, hardware resources included in or controlled by the secure circuit are not accessible by other elements of the device, other than by sending requests to a predetermined set of memory locations (e.g., a secure mailbox).
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公开(公告)号：US11636801B2
公开(公告)日：2023-04-25
申请号：US17308823
申请日：2021-05-05
Applicant: Apple Inc.
Inventor： Reese A. Schreiber , Carlos M. Calderon , Collin L. Pieper , Ian P. Shaeffer , Jeffrey R. Wilcox , Robert L. Ridenour
Abstract: An exemplary computer console can generate one or more video streams having image data relating to an image or a series of images, also referred to as video, to be presented by an electronic display device. The exemplary computer console can provide the one or more video streams to the electronic display device over one or more transport streams. The exemplary computer console can effectively throttle a video stream bitrate of the one or more video streams to be less than of the standard defined transport stream bitrate of the one or more transport streams to allow the transport of the one or more video streams over the one or more transport streams.
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公开(公告)号：US20220057845A1
公开(公告)日：2022-02-24
申请号：US17444269
申请日：2021-08-02
Applicant: Apple Inc.
Inventor： Michael E. Leclerc , Brett W. Degner , Ian P. Shaeffer
Abstract: A computing device can include an enclosure that defines an internal volume and an external surface. An input component can be positioned at the external surface. A processing unit and a memory can be communicatively coupled and disposed within the internal volume. A singular input/output port can be positioned at an orifice defined by the enclosure. The singular input/output port can be communicatively coupled to the processing unit and the memory. The singular input/output port can be configured to receive data and power and configured to output data from the processing unit. The computing device can include an air-moving apparatus to move air along an airflow pathway. The enclosure can include a thermally conductive base.
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Patent Agency Ranking
公开(公告)号：US20190026501A1
公开(公告)日：2019-01-24
申请号：US16128396
申请日：2018-09-11
Applicant: Apple Inc.
Inventor： Pierre-Olivier J. Martel , Jeffrey R. Wilcox , Ian P. Shaeffer , Andrew D. Myrick , Robert W. Hill , Tristan F. Schaap
Abstract: Techniques are disclosed in which a secure circuit controls a gating circuit to enable or disable other circuitry of a device (e.g., one or more input sensors). For example, the gating circuit may be a power gating circuit and the secure circuit may be configured to disable power to an input sensor in certain situations. As another example, the gating circuit may be a clock gating circuit and the secure circuit may be configured to disable the clock to an input sensor. As yet another example, the gating circuit may be configured to gate a control bus and the secure circuit may be configured to disable control signals to an input sensor. In some embodiments, hardware resources included in or controlled by the secure circuit are not accessible by other elements of the device, other than by sending requests to a predetermined set of memory locations (e.g., a secure mailbox).
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公开(公告)号：US20180349649A1
公开(公告)日：2018-12-06
申请号：US15720736
申请日：2017-09-29
Applicant: Apple Inc.
Inventor： Pierre-Olivier J. Martel , Jeffrey R. Wilcox , Ian P. Shaeffer , Andrew D. Myrick , Robert W. Hill , Tristan F. Schaap
CPC classification number: G06F21/71 , G06F1/3237 , G06F1/3287 , G06F21/57 , G06F21/62 , G06F2221/2111 , G06F2221/2141 , G06F2221/2151 , H01L23/57 , H04L63/0861 , H04L63/107 , H04L63/108
Abstract: Techniques are disclosed in which a secure circuit controls a gating circuit to enable or disable other circuity of a device (e.g., one or more input sensors). For example, the gating circuit may be a power gating circuit and the secure circuit may be configured to disable power to an input sensor in certain situations. As another example, the gating circuit may be a clock gating circuit and the secure circuit may be configured to disable the clock to an input sensor. As yet another example, the gating circuit may be configured to gate a control bus and the secure circuit may be configured to disable control signals to an input sensor. In some embodiments, hardware resources included in or controlled by the secure circuit are not accessible by other elements of the device, other than by sending requests to a predetermined set of memory locations (e.g., a secure mailbox).
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公开(公告)号：US11188141B2
公开(公告)日：2021-11-30
申请号：US16127530
申请日：2018-09-11
Applicant: Apple Inc.
Inventor： Corey N. Axelowitz , William R. Allan, II , Eric C. Gaertner , Ian P. Shaeffer , Ronald P. Songco , John T. Orchard
IPC: G06F1/3296 , G06F1/3237 , H02M7/06
Abstract: Circuits, methods, and apparatus that may determine one or more characteristics relating to a mains power supply received by a computer system, and may then determine a maximum amount of power that may be drawn by the computer system given the determined characteristics. An example may provide a computer system having a power supply circuit that may include a detection circuit to receive a mains power supply and to detect a characteristic of the mains power supply. In response to the detected characteristic, the detection circuit may provide an output to a circuit in the computer system that sets a limit on a current that may be drawn by the circuit. In this example, the characteristic may be an RMS value of the mains power supply waveform, a location of where the mains power supply is being received, a quality of the mains power supply, or other characteristic.
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公开(公告)号：US20220269640A1
公开(公告)日：2022-08-25
申请号：US17668512
申请日：2022-02-10
Applicant: Apple Inc.
Inventor： Ian P. Shaeffer , Eric C. Gaertner , John T. Orchard , Michael W. Murphy , Ronald P. Songco , Corey N. Axelowitz , Brett W. Degner
Abstract: A computer includes a processor, a PCIe-compatible interface bus that includes a root that is connected to the processor, and a routing complex that is connected to the root and is controlled by the processor. The computer also includes a first interface slot that is connectable to the root by the switches, a second interface slot that is connectable to the root by the switches, and an extended interface slot that is connectable to the root by the switches. The switches are configured based on properties of a first peripheral device to define a first switching configuration when the first peripheral device is connected only to the first interface slot and to define a second switching configuration when the first peripheral device is connected to both of the first interface slot and the extended interface slot.
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公开(公告)号：US10747908B2
公开(公告)日：2020-08-18
申请号：US16128396
申请日：2018-09-11
Applicant: Apple Inc.
Inventor： Pierre-Olivier J. Martel , Jeffrey R. Wilcox , Ian P. Shaeffer , Andrew D. Myrick , Robert W. Hill , Tristan F. Schaap
Abstract: Techniques are disclosed in which a secure circuit controls a gating circuit to enable or disable other circuitry of a device (e.g., one or more input sensors). For example, the gating circuit may be a power gating circuit and the secure circuit may be configured to disable power to an input sensor in certain situations. As another example, the gating circuit may be a clock gating circuit and the secure circuit may be configured to disable the clock to an input sensor. As yet another example, the gating circuit may be configured to gate a control bus and the secure circuit may be configured to disable control signals to an input sensor. In some embodiments, hardware resources included in or controlled by the secure circuit are not accessible by other elements of the device, other than by sending requests to a predetermined set of memory locations (e.g., a secure mailbox).
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