公开(公告)号：US20230040198A1

公开(公告)日：2023-02-09

申请号：US17396453

申请日：2021-08-06

Applicant: Applied Materials, Inc.

Inventor： Tamer COSKUN ,  Aidyn KEMELDINOV ,  Chung-Shin KANG ,  Uwe HOLLERBACH ,  Thomas L. LAIDIG

IPC: G06F30/392 ,  H01L21/68 ,  G06N20/00

Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.

公开(公告)号：US20240249062A1

公开(公告)日：2024-07-25

申请号：US18439287

申请日：2024-02-12

Applicant: Applied Materials, Inc.

Inventor： Tamer COSKUN ,  Aidyn KEMELDINOV ,  Chung-Shin KANG ,  Uwe HOLLERBACH ,  Thomas L. LAIDIG

IPC: G06F30/392 ,  G06N20/00 ,  H01L21/68

CPC classification number: G06F30/392 ,  G06N20/00 ,  H01L21/68

Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.

公开(公告)号：US20230408932A1

公开(公告)日：2023-12-21

申请号：US18034903

申请日：2021-11-30

Applicant: Applied Materials, Inc.

Inventor： Tamer COSKUN ,  Yen-Shuo LIN ,  Aidyn KEMELDINOV

IPC: G03F7/00 ,  G03F9/00 ,  G06V10/75 ,  G06V10/764 ,  G06T7/73 ,  G06T7/33 ,  G06T7/00

CPC classification number: G03F7/706841 ,  G03F9/7092 ,  G06V10/7515 ,  G06V10/764 ,  G06T7/73 ,  G06T7/337 ,  G06T7/001 ,  G06T2207/30204 ,  G06T2207/20081 ,  G06T2207/30148

Abstract: Embodiments described herein relate to a system, methods, and non-transitory computer-readable mediums that accurately align subsequent patterned layers in a photoresist utilizing a deep learning model and utilizing device patterns to replace alignment marks in lithography processes. The deep learning model is trained to recognize unique device patterns called alignment patterns in the FOV of the camera. Cameras in the lithography system capture images of the alignment patterns. The deep learning model finds the alignment patterns in the field of view of the cameras. An ideal image generated from a design file is matched with the camera with respect to the center of the field of view of the camera. A shift model and a rotation model are output from the deep learning model to create an alignment model. The alignment model is applied to the currently printing layer.