公开(公告)号：US20190019769A1

公开(公告)日：2019-01-17

申请号：US16133512

申请日：2018-09-17

Applicant: Applied Materials, Inc.

Inventor： Tamer COSKUN ,  Jang Fung CHEN

IPC: H01L23/00 ,  H01L21/66 ,  G03F7/20

Abstract: In one embodiment of the invention, a method for correcting a pattern placement on a substrate is disclosed. The method begins by detecting three reference points for a substrate. A plurality of sets of three die location points are detected, each set indicative of an orientation of a die structure, the plurality of sets include a first set associated with a first dies and a second set associated with a second die. A local transformation is calculated for the orientation of the first die and the second on the substrate. Three orientation points are selected from the plurality of sets of three die location points wherein the orientation points are not set members of the same die. A first global orientation of the substrate is calculated from the selected three points from the set of points and the first global transformation and the local transformation for the substrate are stored.

公开(公告)号：US20230040198A1

公开(公告)日：2023-02-09

申请号：US17396453

申请日：2021-08-06

Applicant: Applied Materials, Inc.

Inventor： Tamer COSKUN ,  Aidyn KEMELDINOV ,  Chung-Shin KANG ,  Uwe HOLLERBACH ,  Thomas L. LAIDIG

IPC: G06F30/392 ,  H01L21/68 ,  G06N20/00

Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.

公开(公告)号：US20220382171A1

公开(公告)日：2022-12-01

申请号：US17754072

申请日：2019-10-08

Applicant: Applied Materials, Inc.

Inventor： Tamer COSKUN ,  Jang Fung CHEN ,  Douglas Joseph VAN DEN BROEKE

IPC: G03F7/20

Abstract: Embodiments of the present disclosure relate to a system, a software application, and a method of a lithography process to update one or more of a mask pattern, maskless lithography device parameters, lithography process parameters utilizing a file readable by each of the components of a lithography environment. The file readable by each of the components of a lithography environment stores and shares textual data and facilitates communication between of the components of a lithography environment such that the mask pattern corresponds to a pattern to be written is updated, the maskless lithography device of the lithography environment is calibrated, and process parameters of the lithography process are corrected for accurate writing of the mask pattern on successive substrates.

公开(公告)号：US20200264514A1

公开(公告)日：2020-08-20

申请号：US16277805

申请日：2019-02-15

Applicant: Applied Materials, Inc.

Inventor： Tamer COSKUN ,  Muhammet POYRAZ ,  Qin ZHONG ,  Pacha MONGKOLWONGROJN

IPC: G03F7/20

Abstract: The present disclosure generally relates to photolithography systems, and methods for correcting positional errors in photolithography systems. When a photolithography system is first started, the system enters a stabilization period. During the stabilization period, positional readings and data, such as temperature, pressure, and humidity data, are collected as the system prints or exposes a substrate. A model is created based on the collected data and the positional readings. The model is then used to estimate errors in subsequent stabilization periods, and the estimated errors are dynamically corrected during the subsequent stabilization periods.

公开(公告)号：US20230296987A1

公开(公告)日：2023-09-21

申请号：US18019054

申请日：2021-08-06

Applicant: Applied Materials, Inc.

Inventor： YenShuo LIN ,  Tamer COSKUN

IPC: G03F7/20 ,  G06N5/022

CPC classification number: G03F7/70508 ,  G06N5/022 ,  G03F7/2051 ,  G03F7/70516 ,  G03F7/70525

Abstract: Methods and systems for predictively determining tool drift in a digital lithography tool for early warning, and/or adjusting the tool in-situ to mitigate the effects of drift. Drift is measured during manufacturing by measuring alignment marks from eye-to-eye a bridge-to-bridge, among other methods. Measured drift is decomposed into three components: trend—trending drift over time, increment—rate of change of drift over time, and remaining—the difference between the drift, the trend, and the increment. Each component is provided to a machine learning engine, that predicts the next measurement of each component. Predicted measurements may be provided to the tool for use as adjustment parameters to modify how an eye module shoots a pattern onto a substrate, and/or as an early warning when predicted parameters are outside of a desired processing parameter window.

公开(公告)号：US20190033729A1

公开(公告)日：2019-01-31

申请号：US16146951

申请日：2018-09-28

Applicant: Applied Materials, Inc.

Inventor： Tamer COSKUN ,  Hwan J. JEONG

IPC: G03F7/20

Abstract: Methods are provided and generally relate to adjusting exposure parameters of a substrate in response to an overlay error. The method includes partitioning the substrate into one or more sections. Each section corresponds to an image projection system. A total overlay error of a first layer deposited on the substrate is determined. For each section, a sectional overlay error is calculated. For each overlap area, in which two or more sections overlap, an average overlay error is calculated. The exposure parameters are adjusted in response to the total overlay error.

公开(公告)号：US20180329310A1

公开(公告)日：2018-11-15

申请号：US15595497

申请日：2017-05-15

Applicant: Applied Materials, Inc.

Inventor： Tamer COSKUN ,  Thomas L. LAIDIG ,  Jang Fung CHEN

IPC: G03F7/20 ,  G03F7/00 ,  G03F1/70 ,  G03F1/36

CPC classification number: G03F7/70433 ,  G03F1/36 ,  G03F1/70 ,  G03F7/0002 ,  G03F7/705 ,  G03F2007/2067

Abstract: Methods and systems are provided that, in some embodiments, print and process a layer. The layer can be on a wafer or on an application panel. Thereafter, locations of the features that were actually printed and processed are measured. Based upon differences between the measured differences and designed locations for those features at least one distortion model is created. Each distortion model is inverted to create a corresponding correction model. When there are multiple sections, a distortion model and a correction model can be created for each section. Multiple correction models can be combined to create a global correction model.

公开(公告)号：US20190064683A1

公开(公告)日：2019-02-28

申请号：US15686815

申请日：2017-08-25

Applicant: Applied Materials, Inc.

Inventor： Tamer COSKUN ,  Qin ZHONG

IPC: G03F9/00 ,  G03F7/20

Abstract: Methods are provided that, in some embodiments that provide alignment of a first layer of a printing plate on a chuck. For example, in one embodiment, images of reference marks on a chuck are captured to determine the initial positions of the reference marks on the chuck. A reference model is created from those initial positions. Images of alignment marks on a reference plate are captured and the locations of the alignment marks are determined. A reference plate model is created from the positions of the alignment marks. A mapping model is then created from the reference model and the reference plate model.

公开(公告)号：US20180024444A1

公开(公告)日：2018-01-25

申请号：US15644284

申请日：2017-07-07

Applicant: Applied Materials, Inc.

Inventor： Tamer COSKUN ,  Hwan J. JEONG

IPC: G03F7/20

CPC classification number: G03F7/70633

Abstract: Embodiments disclosed herein generally relate to adjusting exposure parameters of a substrate in response to an overlay error. The method includes partitioning the substrate into one or more sections. Each section corresponds to an image projection system. A total overlay error of a first layer deposited on the substrate is determined. For each section, a sectional overlay error is calculated. For each overlap area, in which two or more sections overlap, an average overlay error is calculated. The exposure parameters are adjusted in response to the total overlay error.

公开(公告)号：US20240249062A1

公开(公告)日：2024-07-25

申请号：US18439287

申请日：2024-02-12

Applicant: Applied Materials, Inc.

Inventor： Tamer COSKUN ,  Aidyn KEMELDINOV ,  Chung-Shin KANG ,  Uwe HOLLERBACH ,  Thomas L. LAIDIG

IPC: G06F30/392 ,  G06N20/00 ,  H01L21/68

CPC classification number: G06F30/392 ,  G06N20/00 ,  H01L21/68

Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.