FAULT DETECTION CLASSIFICATION
    1.
    发明申请

    公开(公告)号:US20190108422A1

    公开(公告)日:2019-04-11

    申请号:US15726145

    申请日:2017-10-05

    Inventor: Dermot CANTWELL

    Abstract: Embodiments disclosed herein generally relate to a method, system, and non-transitory computer readable medium for classifying an outlier in time series data collected by a sensor positioned in a substrate processing chamber. The client device receives time series data from the sensor positioned in the substrate processing chamber. The client device converts the time series data to a bounded uniform signal. The client device identifies signal sub-segments that do not match an expected behavior. The client device classifies the identified sub-segments that do not match the expected behavior.

    ADAPTIVE CONTROL OF VARIABILITY IN DEVICE PERFORMANCE IN ADVANCED SEMICONDUCTOR PROCESSES

    公开(公告)号:US20210175104A1

    公开(公告)日:2021-06-10

    申请号:US17182119

    申请日:2021-02-22

    Abstract: Systems and methods for controlling device performance variability during manufacturing of a device on wafers are disclosed. The system includes a process platform, on-board metrology (OBM) tools, and a first server that stores a machine-learning based process control model. The first server combines virtual metrology (VM) data and OBM data to predict a spatial distribution of one or more dimensions of interest on a wafer. The system further comprises an in-line metrology tool, such as SEM, to measure the one or more dimensions of interest on a subset of wafers sampled from each lot. A second server having a machine-learning engine receives from the first server the predicted spatial distribution of the one or more dimensions of interest based on VM and OBM, and also receives SEM metrology data, and updates the process control model periodically (e.g., wafer-to-wafer, lot-to-lot, chamber-to-chamber etc.) using machine learning techniques.

    PREDICTIVE SPATIAL DIGITAL DESIGN OF EXPERIMENT FOR ADVANCED SEMICONDUCTOR PROCESS OPTIMIZATION AND CONTROL

    公开(公告)号:US20200279066A1

    公开(公告)日:2020-09-03

    申请号:US16876991

    申请日:2020-05-18

    Abstract: This disclosure describes methods and systems for building a spatial model to predict performance of processing chamber, and using the spatial model to converge faster to a desired process during the process development phase. Specifically, a machine-learning engine obtains an empirical process model for a given process for a given processing chamber. The empirical process model is calibrated by using the in-line metrology data as reference. A predictive model is built by refining the empirical process model by a machine-learning engine that receives customized metrology data and outputs one or more spatial maps of the wafer for one or more dimensions of interest across the wafer without physically processing any further wafers, i.e. by performing spatial digital design of experiment (Spatial DoE).

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