公开(公告)号：US20220199804A1

公开(公告)日：2022-06-23

申请号：US17690193

申请日：2022-03-09

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Tushar Mandrekar ,  Patricia M. Liu ,  Suketu Arun Parikh ,  Matthias Bauer ,  Dimitri R. Kioussis ,  Sanjay Natarajan ,  Abhishek Dube

IPC: H01L29/66 ,  H01L21/687 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/67 ,  H01L21/677 ,  H01L29/08

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

公开(公告)号：US20200013878A1

公开(公告)日：2020-01-09

申请号：US16502555

申请日：2019-07-03

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Tushar Mandrekar ,  Patricia M. Liu ,  Suketu Arun Parikh ,  Matthias Bauer ,  Dimitri R. Kioussis ,  Sanjay Natarajan ,  Abhishek Dube

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/67 ,  H01L21/677 ,  H01L21/687

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

公开(公告)号：US11309404B2

公开(公告)日：2022-04-19

申请号：US16502555

申请日：2019-07-03

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Tushar Mandrekar ,  Patricia M. Liu ,  Suketu Arun Parikh ,  Matthias Bauer ,  Dimitri R. Kioussis ,  Sanjay Natarajan ,  Abhishek Dube

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/687 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/67 ,  H01L21/677 ,  H01L29/08

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.