公开(公告)号：US11309404B2

公开(公告)日：2022-04-19

申请号：US16502555

申请日：2019-07-03

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Tushar Mandrekar ,  Patricia M. Liu ,  Suketu Arun Parikh ,  Matthias Bauer ,  Dimitri R. Kioussis ,  Sanjay Natarajan ,  Abhishek Dube

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/687 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/67 ,  H01L21/677 ,  H01L29/08

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

公开(公告)号：US12125698B2

公开(公告)日：2024-10-22

申请号：US17516326

申请日：2021-11-01

Applicant: Applied Materials, Inc.

Inventor： Lara Hawrylchak ,  Schubert S. Chu ,  Tushar Mandrekar ,  Errol C. Sanchez ,  Kin Pong Lo

IPC: H01L21/02 ,  B08B7/00 ,  C23C16/02 ,  C23C16/24 ,  C23C16/30 ,  C23C16/455 ,  C23C16/505 ,  C23C16/54 ,  C30B25/02 ,  H01J37/32 ,  H01L21/3213 ,  H01L21/67 ,  H01L21/687

CPC classification number: H01L21/02049 ,  B08B7/0035 ,  C23C16/0209 ,  C23C16/0245 ,  C23C16/24 ,  C23C16/30 ,  C23C16/45565 ,  C23C16/505 ,  C23C16/54 ,  C30B25/02 ,  H01J37/32082 ,  H01J37/32357 ,  H01J37/32513 ,  H01J37/32522 ,  H01J37/32899 ,  H01L21/02046 ,  H01L21/02315 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/32136 ,  H01L21/67103 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/67184 ,  H01L21/67207 ,  H01L21/67248 ,  H01L21/68742 ,  H01J2237/334 ,  H01J2237/335

Abstract: Implementations of the present disclosure generally relates to a transfer chamber coupled to at least one vapor phase epitaxy chamber a plasma oxide removal chamber coupled to the transfer chamber, the plasma oxide removal chamber comprising a lid assembly with a mixing chamber and a gas distributor; a first gas inlet formed through a portion of the lid assembly and in fluid communication with the mixing chamber; a second gas inlet formed through a portion of the lid assembly and in fluid communication with the mixing chamber; a third gas inlet formed through a portion of the lid assembly and in fluid communication with the mixing chamber; and a substrate support with a substrate supporting surface; a lift member disposed in a recess of the substrate supporting surface and coupled through the substrate support to a lift actuator; and a load lock chamber coupled to the transfer chamber.

公开(公告)号：US20220199804A1

公开(公告)日：2022-06-23

申请号：US17690193

申请日：2022-03-09

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Tushar Mandrekar ,  Patricia M. Liu ,  Suketu Arun Parikh ,  Matthias Bauer ,  Dimitri R. Kioussis ,  Sanjay Natarajan ,  Abhishek Dube

IPC: H01L29/66 ,  H01L21/687 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/67 ,  H01L21/677 ,  H01L29/08

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

公开(公告)号：US11164737B2

公开(公告)日：2021-11-02

申请号：US16100399

申请日：2018-08-10

Applicant: Applied Materials, Inc.

Inventor： Lara Hawrylchak ,  Schubert S. Chu ,  Tushar Mandrekar ,  Errol C. Sanchez ,  Kin Pong Lo

IPC: H01L21/02 ,  C30B25/02 ,  C23C16/02 ,  B08B7/00 ,  H01J37/32 ,  C23C16/24 ,  H01L21/67 ,  C23C16/30 ,  C23C16/54 ,  H01L21/687 ,  C23C16/455 ,  C23C16/505 ,  H01L21/3213

Abstract: Implementations of the present disclosure generally relates to a transfer chamber coupled to at least one vapor phase epitaxy chamber a plasma oxide removal chamber coupled to the transfer chamber, the plasma oxide removal chamber comprising a lid assembly with a mixing chamber and a gas distributor; a first gas inlet formed through a portion of the lid assembly and in fluid communication with the mixing chamber; a second gas inlet formed through a portion of the lid assembly and in fluid communication with the mixing chamber; a third gas inlet formed through a portion of the lid assembly and in fluid communication with the mixing chamber; and a substrate support with a substrate supporting surface; a lift member disposed in a recess of the substrate supporting surface and coupled through the substrate support to a lift actuator; and a load lock chamber coupled to the transfer chamber.

公开(公告)号：US11049719B2

公开(公告)日：2021-06-29

申请号：US16057213

申请日：2018-08-07

Applicant: Applied Materials, Inc.

Inventor： Lara Hawrylchak ,  Kin Pong Lo ,  Errol C. Sanchez ,  Schubert S. Chu ,  Tushar Mandrekar

IPC: C30B25/18 ,  H01L21/02 ,  C23C16/02 ,  B08B7/00 ,  H01L21/67 ,  H01J37/32 ,  H01L21/687 ,  C30B25/02 ,  C23C16/54 ,  C30B33/08 ,  C23C16/24 ,  C23C16/46

Abstract: In one implementation, a processing system includes a first transfer chamber coupling to at least one epitaxy process chamber, a second transfer chamber, a transition station disposed between the first transfer chamber and the second transfer chamber, a first plasma chamber coupled to the second transfer chamber for removing oxides from a surface of a substrate, and a load lock chamber coupled to the second transfer chamber. The transition station connects to the first transfer chamber and the second transfer chamber, and the transition station includes a second plasma chamber for removing contaminants from the surface of the substrate.

公开(公告)号：US20200013878A1

公开(公告)日：2020-01-09

申请号：US16502555

申请日：2019-07-03

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Tushar Mandrekar ,  Patricia M. Liu ,  Suketu Arun Parikh ,  Matthias Bauer ,  Dimitri R. Kioussis ,  Sanjay Natarajan ,  Abhishek Dube

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/67 ,  H01L21/677 ,  H01L21/687

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.