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公开(公告)号：US11462411B2
公开(公告)日：2022-10-04
申请号：US17242375
申请日：2021-04-28
发明人： Gaurav Thareja , Keyvan Kashefizadeh , Xikun Wang , Anchuan Wang , Sanjay Natarajan , Sean M. Seutter , Dong Wu
IPC分类号： H01L21/283 , H01L29/49 , H01L21/28 , H01L29/45
摘要： A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.
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公开(公告)号：US11171141B2
公开(公告)日：2021-11-09
申请号：US16804226
申请日：2020-02-28
发明人： Priyadarshi Panda , Seshadri Ganguli , Sang Ho Yu , Sung-Kwan Kang , Gill Yong Lee , Sanjay Natarajan , Rajib Lochan Swain , Jorge Pablo Fernandez
IPC分类号： H01L27/108
摘要： Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.
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公开(公告)号：US11152479B2
公开(公告)日：2021-10-19
申请号：US16773848
申请日：2020-01-27
发明人： Gaurav Thareja , Xuebin Li , Abhishek Dube , Yi-Chiau Huang , Andy Lo , Patricia M. Liu , Sanjay Natarajan , Saurabh Chopra
IPC分类号： H01L29/45 , H01L29/08 , H01L29/40 , H01L29/78 , H01L29/417
摘要： The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing chamber. The method includes forming a source/drain region in a processing system, forming a doped semiconductor layer on the source/drain region in the processing system, forming a metal silicide layer, forming a dielectric material, forming a trench in the dielectric material, and filling the trench with a conductor. The source/drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking vacuum. A semiconductor device includes a plurality of layers, and the semiconductor device has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device. Embodiments of the present disclosure enable formation of a source/drain contact with reduced contact resistance by using integrated processes, which allows various operations of the source/drain contact formation to be performed within the same processing system.
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公开(公告)号：US11114320B2
公开(公告)日：2021-09-07
申请号：US16690988
申请日：2019-11-21
发明人： Gaurav Thareja , Takashi Kuratomi , Avgerinos V. Gelatos , Xianmin Tang , Sanjay Natarajan , Keyvan Kashefizadeh , Zhebo Chen , Jianxin Lei , Shashank Sharma
摘要： Embodiments disclosed herein include a processing system and a method of forming a contact. The processing system includes a plurality of process chambers configured to deposit, etch, and/or anneal a source/drain region of a substrate. The method includes depositing a doped semiconductor layer over a source/drain region, forming an anchor layer in a trench, and depositing a conductor in the trench. The method of forming a contact results in reduced contact resistance by using integrated processes, which allows various operations of the source/drain contact formation to be performed within the same processing system.
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公开(公告)号：US11004687B2
公开(公告)日：2021-05-11
申请号：US16442797
申请日：2019-06-17
发明人： Gaurav Thareja , Keyvan Kashefizadeh , Xikun Wang , Anchuan Wang , Sanjay Natarajan , Sean M. Seutter , Dong Wu
IPC分类号： H01L21/28 , H01L29/49 , H01L29/45 , H01L21/283
摘要： A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.
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公开(公告)号：US20190385851A1
公开(公告)日：2019-12-19
申请号：US16444856
申请日：2019-06-18
发明人： SRINIVAS GANDIKOTA , Abhijit Basu Mallick , Swaminathan Srinivasan , Rui Cheng , Susmit Singha Roy , Gaurav Thareja , Mukund Srinivasan , Sanjay Natarajan
IPC分类号： H01L21/225 , H01L21/30 , H01L21/02 , H01L21/67
摘要： Methods of doping a semiconductor material are disclosed. Some embodiments provide for conformal doping of three dimensional structures. Some embodiments provide for doping with high concentrations of boron for p-type doping.
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公开(公告)号：US11749315B2
公开(公告)日：2023-09-05
申请号：US17551538
申请日：2021-12-15
发明人： Chang Seok Kang , Tomohiko Kitajima , Gill Yong Lee , Sanjay Natarajan , Sung-Kwan Kang , Lequn Liu
CPC分类号： G11C5/063 , H10B12/02 , H10B12/03 , H10B12/0335 , H10B12/05 , H10B12/30 , H10B12/318 , H10B12/482 , H10B12/488
摘要： Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.
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公开(公告)号：US20230039074A1
公开(公告)日：2023-02-09
申请号：US17968068
申请日：2022-10-18
IPC分类号： H01L29/66 , H01L29/06 , H01L29/423
摘要： Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.
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公开(公告)号：US20220246432A1
公开(公告)日：2022-08-04
申请号：US17724994
申请日：2022-04-20
发明人： Srinivas Gandikota , Abhijit Basu Mallick , Swaminathan Srinivasan , Rui Cheng , Susmit Singha Roy , Gaurav Thareja , Mukund Srinivasan , Sanjay Natarajan
IPC分类号： H01L21/225 , H01L21/30 , H01L21/67 , H01L21/02
摘要： Methods of doping a semiconductor material are disclosed. Some embodiments provide for conformal doping of three dimensional structures. Some embodiments provide for doping with high concentrations of boron for p-type doping.
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公开(公告)号：US20220108728A1
公开(公告)日：2022-04-07
申请号：US17551538
申请日：2021-12-15
发明人： Chang Seok Kang , Tomohiko Kitajima , Gill Yong Lee , Sanjay Natarajan , Sung-Kwan Kang , Lequn Liu
IPC分类号： G11C5/06 , H01L27/108
摘要： Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.
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