公开(公告)号：US20230146831A1

公开(公告)日：2023-05-11

申请号：US17902838

申请日：2022-09-04

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Gill Yong Lee ,  Fred Fishburn ,  Tomohiko Kitajima ,  Sung-Kwan Kang ,  Sony Varghese

IPC: H01L23/528 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76895 ,  H01L23/535

Abstract: A semiconductor manufacturing process for forming a three-dimensional (3D) memory structure and a semiconductor device having a 3D memory structure is described. The 3D memory structure comprises layers of memory cells with L shaped conductive layers where the L shaped conductive layers of each layer are coupled to metal lines disposed above the top or upper most layer such that the memory cells in each layer can be coupled to control circuitry.

公开(公告)号：US20230101155A1

公开(公告)日：2023-03-30

申请号：US17868156

申请日：2022-07-19

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Fred Fishburn ,  Tomohiko Kitajima ,  Sung-Kwan Kang ,  Sony Varghese ,  Gill Yong Lee

IPC: H01L27/108

Abstract: A memory device architecture, and method of fabricating a three dimensional device are provided. The memory device architecture may include a plurality of memory blocks, arranged in an array, wherein a given memory block comprises: a cell region, the cell region comprising a three-dimensional array of memory cells, arranged in a plurality of n memory cell layers; and a staircase region, the staircase region being disposed adjacent to at least a first side of the cell region, the staircase region comprising a signal line assembly that is coupled to the three-dimensional array of memory cells.

公开(公告)号：US20220336470A1

公开(公告)日：2022-10-20

申请号：US17829939

申请日：2022-06-01

Applicant: Applied Materials, Inc.

Inventor： Sony Varghese ,  Fred Fishburn

IPC: H01L27/108

Abstract: Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.

公开(公告)号：US11980021B2

公开(公告)日：2024-05-07

申请号：US17829939

申请日：2022-06-01

Applicant: Applied Materials, Inc.

Inventor： Sony Varghese ,  Fred Fishburn

IPC: H10B12/00

CPC classification number: H10B12/09 ,  H10B12/03 ,  H10B12/05 ,  H10B12/30 ,  H10B12/50

Abstract: Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.

公开(公告)号：US11380691B1

公开(公告)日：2022-07-05

申请号：US17230591

申请日：2021-04-14

Applicant: Applied Materials, Inc.

Inventor： Sony Varghese ,  Fred Fishburn

IPC: H01L27/108

Abstract: Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.