公开(公告)号：US11621266B2

公开(公告)日：2023-04-04

申请号：US17522448

申请日：2021-11-09

申请人： Applied Materials, Inc.

发明人： Priyadarshi Panda ,  Seshadri Ganguli ,  Sang Ho Yu ,  Sung-Kwan Kang ,  Gill Yong Lee ,  Sanjay Natarajan ,  Rajib Lochan Swain ,  Jorge Pablo Fernandez

IPC分类号： H01L21/67 ,  H01L27/108

摘要： Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.

公开(公告)号：US20230040627A1

公开(公告)日：2023-02-09

申请号：US17879097

申请日：2022-08-02

申请人： Applied Materials, Inc.

发明人： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Sung-Kwan Kang

IPC分类号： H01L27/11524 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

摘要： Described is a semiconductor memory device and methods of manufacture. The semiconductor memory device comprises a memory array comprising at least one select-gate-for-drain (SGD) transistor and at least one memory transistor, the memory array having at least one strapping region and at least one strapping contact, the strapping contact connecting a select-gate-for-drain (SGD) transistor to a strapping line.

公开(公告)号：US20220415651A1

公开(公告)日：2022-12-29

申请号：US17361925

申请日：2021-06-29

申请人： Applied Materials, Inc.

发明人： Qixin Shen ,  Chuanxi Yang ,  Hang Yu ,  Deenesh Padhi ,  Gill Yong Lee ,  Sung-Kwan Kang ,  Abdul Wahab Mohammed ,  Hailing Liu

IPC分类号： H01L21/02 ,  H01L21/033 ,  H01L27/108

摘要： Memory devices and methods of forming memory devices are described. The memory devices comprise a silicon nitride hard mask layer on a ruthenium layer. Forming the silicon nitride hard mask layer on the ruthenium comprises pre-treating the ruthenium layer with a plasma to form an interface layer on the ruthenium layer; and forming a silicon nitride layer on the interface layer by plasma-enhanced chemical vapor deposition (PECVD). Pre-treating the ruthenium layer, in some embodiments, results in the interface layer having a reduced roughness and the memory device having a reduced resistivity compared to a memory device that does not include the interface layer.

公开(公告)号：US20220352176A1

公开(公告)日：2022-11-03

申请号：US17727907

申请日：2022-04-25

申请人： Applied Materials, Inc.

发明人： Sung-Kwan Kang ,  Fredrick Fishburn ,  Abdul Wahab Mohammed ,  Gill Yong Lee

IPC分类号： H01L27/108

摘要： Memory devices and methods of forming memory devices are described. Methods of forming electronic devices are described where a spacer is formed around each of the bit line contact pillars, the spacer in contact with the spacer of an adjacent bit line contact pillar. A doped layer is then epitaxially grown on the memory stack and bit line is formed on the memory stack. The bit line is self-aligned with the active region.

公开(公告)号：US20200251151A1

公开(公告)日：2020-08-06

申请号：US16779830

申请日：2020-02-03

申请人： Applied Materials, Inc.

发明人： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Sanjay Natarajan ,  Sung-Kwan Kang ,  Lequn Liu

IPC分类号： G11C5/06 ,  H01L27/108

摘要： Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

公开(公告)号：US11552082B2

公开(公告)日：2023-01-10

申请号：US17002415

申请日：2020-08-25

申请人： Applied Materials, Inc.

发明人： Sung-Kwan Kang ,  Gill Yong Lee ,  Sang Ho Yu ,  Shih Chung Chen ,  Jeffrey W. Anthis

IPC分类号： H01L21/3213 ,  H01L21/28 ,  H01L21/321 ,  H01L21/02 ,  H01L27/108 ,  H01L29/49 ,  H01L29/423

摘要： Memory devices and methods of forming memory devices are described. The memory devices comprise two work-function metal layers, where one work-function layer has a lower work-function than the other work-function layer. The low work-function layer may reduce gate-induced drain leakage current losses. Methods of forming memory devices are also described.

公开(公告)号：US20220367560A1

公开(公告)日：2022-11-17

申请号：US17741803

申请日：2022-05-11

申请人： Applied Materials, Inc.

发明人： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee

IPC分类号： H01L27/146 ,  H01L21/02

摘要： Memory devices and methods of manufacturing memory devices are provided. The device and methods described decrease the resistivity of word lines by forming word lines comprising low resistivity materials. The low resistivity material has a resistivity in a range of from 5 μΩcm to 100 μΩcm. Low resistivity materials may be formed by recessing the word line and selectively growing the low resistivity materials in the recessed portion of the word line. Alternatively, low resistivity materials may be formed by depositing a metal layer and silicidating the metal in the word line region and in the common source line region.

公开(公告)号：US20220068935A1

公开(公告)日：2022-03-03

申请号：US17522448

申请日：2021-11-09

申请人： Applied Materials, Inc.

发明人： Priyadarshi Panda ,  Seshadri Ganguli ,  Sang Ho Yu ,  Sung-Kwan Kang ,  Gill Yong Lee ,  Sanjay Natarajan ,  Rajib Lochan Swain ,  Jorge Pablo Fernandez

IPC分类号： H01L27/108

摘要： Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.

公开(公告)号：US20200286897A1

公开(公告)日：2020-09-10

申请号：US16804226

申请日：2020-02-28

申请人： Applied Materials, Inc.

发明人： Priyadarshi Panda ,  Seshadri Ganguli ,  Sang Ho Yu ,  Sung-Kwan Kang ,  Gill Yong Lee ,  Sanjay Natarajan ,  Rajib Lochan Swain ,  Jorge Pablo Fernandez

IPC分类号： H01L27/108

摘要： Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.

公开(公告)号：US10700072B2

公开(公告)日：2020-06-30

申请号：US16164236

申请日：2018-10-18

申请人： Applied Materials, Inc.

发明人： Priyadarshi Panda ,  Jianxin Lei ,  Wenting Hou ,  Mihaela Balseanu ,  Ning Li ,  Sanjay Natarajan ,  Gill Yong Lee ,  In Seok Hwang ,  Nobuyuki Sasaki ,  Sung-Kwan Kang

IPC分类号： H01L27/108 ,  H01L21/3213 ,  H01L21/033

摘要： Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.