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    CHIPLET AWARE ADAPTABLE QUANTIZATION
    2.
    发明申请
    CHIPLET AWARE ADAPTABLE QUANTIZATION 有权

    公开(公告)号：US20240403258A1

    公开(公告)日：2024-12-05

    申请号：US18328852

    申请日：2023-06-05

    Applicant: Applied Materials, Inc.

    Inventor： Bilal Shafi Sheikh ,  Tameesh Suri ,  Nathaniel See ,  Sutapa Dutta ,  Yun-Ting Sun ,  Udaykumar Diliprao Hanmante ,  Naveed Zaman

    IPC: G06F15/78 ,  G06N5/04

    Abstract: A chiplet-based architecture may quantize, or reduce, the number of bits at various stages of the data path in an artificial-intelligence processor. This architecture may leverage the synergy between quantizing multiple dimensions together to greatly decrease the memory usage and data path bandwidth. Internal weights may be quantized statically after a training procedure. Accumulator bits and activation bits may be quantized dynamically during an inference operation. New hardware logic may be configured to quantize the outputs of each operation directly from the core or other processing node before the tensor is stored in memory. Quantization may use a statistic from a previous tensor for a current output tensor, while also calculating a statistic to be used on a subsequent output tensor. In addition to quantizing based on a statistic, bits can be further quantized using a Kth percentile clamping operation.

    ROUTER ARCHITECTURE FOR MULTI-DIMENSIONAL TOPOLOGIES IN ON-CHIP AND ON-PACKAGE NETWORKS
    5.
    发明申请
    ROUTER ARCHITECTURE FOR MULTI-DIMENSIONAL TOPOLOGIES IN ON-CHIP AND ON-PACKAGE NETWORKS 有权

    公开(公告)号：US20220400073A1

    公开(公告)日：2022-12-15

    申请号：US17348183

    申请日：2021-06-15

    Applicant: Applied Materials, Inc.

    Inventor： Tameesh Suri ,  Bilal Shafi Sheikh ,  Myron Shak ,  Naveed Zaman

    IPC: H04L12/733 ,  H04L12/741 ,  H04L12/803 ,  H04L12/835 ,  G06K9/62

    Abstract: A router may include input buffers that receive a packet being transmitted from a source to a destination, a state generator that determines a state for the packet, and a memory representing weights for actions corresponding to possible states. The memory may be configured to return an action corresponding to the state of the packet, where the action may indicate a next hop in the route between the source and the destination. The router may also include reward logic configured to generate the weights for the plurality of actions in the memory. The reward logic may receive a global reward corresponding to the route between the source and the destination, calculate a local reward corresponding to next hops available to the router; and combine the global reward and the local reward to generate the weights for the plurality of actions in the memory.

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