HIGH LATERAL TO VERTICAL RATIO ETCH PROCESS FOR DEVICE MANUFACTURING
    2.
    发明申请
    HIGH LATERAL TO VERTICAL RATIO ETCH PROCESS FOR DEVICE MANUFACTURING 审中-公开
    用于设备制造的高级垂直比例蚀刻工艺

    公开(公告)号:US20130319614A1

    公开(公告)日:2013-12-05

    申请号:US13960760

    申请日:2013-08-06

    Abstract: A layer stack over a substrate is etched using a photoresist pattern deposited on the layer stack as a first mask. The photoresist pattern is in-situ cured using plasma. At least a portion of the photoresist pattern can be modified by curing. In one embodiment, silicon by-products are formed on the photoresist pattern from the plasma. In another embodiment, a carbon from the plasma is embedded into the photoresist pattern. In yet another embodiment, the plasma produces an ultraviolet light to cure the photoresist pattern. The cured photoresist pattern is slimmed. The layer stack is etched using the slimmed photoresist pattern as a second mask.

    Abstract translation: 使用沉积在层堆叠上的光致抗蚀剂图案作为第一掩模蚀刻在衬底上的层叠。 使用等离子体原位固化光致抗蚀剂图案。 光致抗蚀剂图案的至少一部分可以通过固化来改性。 在一个实施例中,在等离子体的光刻胶图案上形成硅副产物。 在另一个实施例中,来自等离子体的碳被嵌入到光致抗蚀剂图案中。 在另一个实施例中,等离子体产生紫外光以固化光致抗蚀剂图案。 固化的光致抗蚀剂图案变薄。 使用薄的光致抗蚀剂图案作为第二掩模蚀刻层堆叠。

    HIGH LATERAL TO VERTICAL RATIO ETCH PROCESS FOR DEVICE MANUFACTURING

    公开(公告)号:US20200013610A1

    公开(公告)日:2020-01-09

    申请号:US16576650

    申请日:2019-09-19

    Abstract: A layer stack over a substrate is etched using a photoresist pattern deposited on the layer stack as a first mask. The photoresist pattern is in-situ cured using plasma. At least a portion of the photoresist pattern can be modified by curing. In one embodiment, silicon by-products are formed on the photoresist pattern from the plasma. In another embodiment, a carbon from the plasma is embedded into the photoresist pattern. In yet another embodiment, the plasma produces an ultraviolet light to cure the photoresist pattern. The cured photoresist pattern is slimmed. The layer stack is etched using the slimmed photoresist pattern as a second mask.

    Deep auto-encoder for equipment health monitoring and fault detection in semiconductor and display process equipment tools

    公开(公告)号:US11568198B2

    公开(公告)日:2023-01-31

    申请号:US16545908

    申请日:2019-08-20

    Abstract: Implementations described herein generally relate to a method for detecting anomalies in time-series traces received from sensors of manufacturing tools. A server feeds a set of training time-series traces to a neural network configured to derive a model of the training time-series traces that minimizes reconstruction error of the training time-series traces. The server extracts a set of input time-series traces from one or more sensors associated with one or more manufacturing tools configured to produce a silicon substrate. The server feeds the set of input time-series traces to the trained neural network to produce a set of output time series traces reconstructed based on the model. The server calculates a mean square error between a first input time series trace of the set of input time series traces and a corresponding first output time series trace of the set of output time-series traces. The server declares the sensor corresponding to the first input time-series trace as having an anomaly when the mean square error exceeds a pre-determined value.

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