公开(公告)号：US20240288778A1

公开(公告)日：2024-08-29

申请号：US18115145

申请日：2023-02-28

Applicant: Applied Materials, Inc.

Inventor： Ying-Chiao Wang ,  Thomas L Laidig ,  Chun-Chih Chuang ,  Frederick Lie ,  Chen-Yuan Hsieh ,  Chun-Cheng Yeh

IPC: G03F7/20

CPC classification number: G03F7/704 ,  G03F7/70458 ,  G03F7/70475 ,  G03F7/70525

Abstract: A digital lithography system includes adjacent scan regions, exposure units located above the scan regions, a memory, and a processing device operatively coupled to the memory. The exposure units include a first exposure unit associated with a first scan region and a second exposure unit associated with a second scan region. The processing device is to initiate a digital lithography process to pattern a substrate disposed on a stage in accordance with instructions. The processing device is to further perform a first pass of the first exposure unit over a stitching region at an interface of the first scan region and the second scan region at a first time. The processing device is to further perform a second pass of the second exposure unit over the stitching region at a second time that varies from the first time by less than forty seconds.

公开(公告)号：US12189299B2

公开(公告)日：2025-01-07

申请号：US18115145

申请日：2023-02-28

Applicant: Applied Materials, Inc.

Inventor： Ying-Chiao Wang ,  Thomas L Laidig ,  Chun-Chih Chuang ,  Frederick Lie ,  Chen-Yuan Hsieh ,  Chun-Cheng Yeh

IPC: G03F7/00

Abstract: A digital lithography system includes adjacent scan regions, exposure units located above the scan regions, a memory, and a processing device operatively coupled to the memory. The exposure units include a first exposure unit associated with a first scan region and a second exposure unit associated with a second scan region. The processing device is to initiate a digital lithography process to pattern a substrate disposed on a stage in accordance with instructions. The processing device is to further perform a first pass of the first exposure unit over a stitching region at an interface of the first scan region and the second scan region at a first time. The processing device is to further perform a second pass of the second exposure unit over the stitching region at a second time that varies from the first time by less than forty seconds.

公开(公告)号：US11934762B2

公开(公告)日：2024-03-19

申请号：US17396453

申请日：2021-08-06

Applicant: Applied Materials, Inc.

Inventor： Tamer Coskun ,  Aidyn Kemeldinov ,  Chung-Shin Kang ,  Uwe Hollerbach ,  Thomas L Laidig

IPC: G06F30/39 ,  G06F30/392 ,  G06N20/00 ,  H01L21/68

CPC classification number: G06F30/392 ,  G06N20/00 ,  H01L21/68

Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.