公开(公告)号：US11934762B2

公开(公告)日：2024-03-19

申请号：US17396453

申请日：2021-08-06

Applicant: Applied Materials, Inc.

Inventor： Tamer Coskun ,  Aidyn Kemeldinov ,  Chung-Shin Kang ,  Uwe Hollerbach ,  Thomas L Laidig

IPC: G06F30/39 ,  G06F30/392 ,  G06N20/00 ,  H01L21/68

CPC classification number: G06F30/392 ,  G06N20/00 ,  H01L21/68

Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.

公开(公告)号：US11906905B2

公开(公告)日：2024-02-20

申请号：US17767020

申请日：2019-11-15

Applicant: Applied Materials, Inc.

Inventor： Chung-Shin Kang ,  Yinfeng Dong ,  Rick R. Hung ,  Yao Cheng Yang ,  Tsaichuan Kao

IPC: G03F7/20 ,  G03F7/00

CPC classification number: G03F7/70433 ,  G03F7/70508

Abstract: A verification device for verifying a design file for digital lithography comprises a memory and a controller. The memory comprises the design file. The controller is configured to access the design file and apply one or more compliance rules to the design file to determine compliance of the design file. The compliance rules comprises at least one of detecting non-orthogonal edges within the design file, detecting non-compliant overlapping structures within the design file, and detecting a non-compliant interaction between a reference layer of the design file and a target layer of the design file. The controller is further configured to verify the design file in response to a comparison of a number of non-orthogonal edges, non-compliant overlapping structures and non-compliant interactions to a threshold.

公开(公告)号：US12292693B2

公开(公告)日：2025-05-06

申请号：US18415430

申请日：2024-01-17

Applicant: Applied Materials, Inc.

Inventor： Chung-Shin Kang ,  Jun Yang ,  Hongbin Ji

IPC: G03F7/00

Abstract: In embodiments of a digital lithography system, physical design data prepared at a data prep server in a hierarchical data structure. A leaf node comprises a repeater nod, comprising a bitmap image and a plurality of locations at which the bitmap appears in a physical design. At an EYE server, a repeater node bitmap is adjusted based upon, for example, spatial light modulator rotational adjustment and substrate distortion. The adjusted repeater node and the plurality of locations in which the adjusted repeater appears is compared to the repeater of the data prep server and its plurality of locations. In further embodiments, a rasterizer generates a checksum of bitmap to be printed to a substrate, from the EYE server bitmap. The checksum is compared to a checksum of the EYE server bitmap.

公开(公告)号：US11914305B2

公开(公告)日：2024-02-27

申请号：US17792667

申请日：2020-02-18

Applicant: Applied Materials, Inc.

Inventor： Chung-Shin Kang ,  Jun Yang ,  Hongbin Ji

IPC: G03F7/00

CPC classification number: G03F7/70508 ,  G03F7/704 ,  G03F7/70291

Abstract: In embodiments of a digital lithography system, physical design data prepared at a data prep server in a hierarchical data structure. A leaf node comprises a repeater nod, comprising a bitmap image and a plurality of locations at which the bitmap appears in a physical design. At an EYE server, a repeater node bitmap is adjusted based upon, for example, spatial light modulator rotational adjustment and substrate distortion. The adjusted repeater node and the plurality of locations in which the adjusted repeater appears is compared to the repeater of the data prep server and its plurality of locations. In further embodiments, a rasterizer generates a checksum of bitmap to be printed to a substrate, from the EYE server bitmap. The checksum is compared to a checksum of the EYE server bitmap.

公开(公告)号：US12302641B2

公开(公告)日：2025-05-13

申请号：US17636998

申请日：2019-09-23

Applicant: Applied Materials, Inc.

Inventor： Chung-Shin Kang ,  Thomas L. Laidig ,  Yinfeng Dong ,  Yao-Cheng Yang ,  Chen-Chien Hung ,  Shivaraj Gururaj Kamalapura ,  Tsaichuan Kao

IPC: G06F30/398 ,  G03F7/00 ,  H10D89/10

Abstract: A digital pattern generation system comprises a memory and a controller. The controller is coupled the memory and is configured to remove redundant cells from a digital pattern file, generate a first updated digital pattern file and compare the first updated digital pattern file with the digital pattern file. Further a number of vertexes of a first arc of the first updated digital pattern file is reduced to generate a second updated digital pattern file. Additionally, a first cell of the second updated digital pattern file is replaced with an alternative version of the first cell to generate a third updated digital pattern file. Further, one or more polygons within the third updated digital pattern file is converted to one or more quad polygons to generate an optimized digital pattern file.

公开(公告)号：US12242789B2

公开(公告)日：2025-03-04

申请号：US18439287

申请日：2024-02-12

Applicant: Applied Materials, Inc.

Inventor： Tamer Coskun ,  Aidyn Kemeldinov ,  Chung-Shin Kang ,  Uwe Hollerbach ,  Thomas L. Laidig

IPC: G06F30/39 ,  G06F30/392 ,  G06N20/00 ,  H01L21/68

Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.