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公开(公告)号：US12248254B2
公开(公告)日：2025-03-11
申请号：US17754072
申请日：2019-10-08
Applicant: Applied Materials, Inc.
Inventor： Tamer Coskun , Jang Fung Chen , Douglas Joseph Van Den Broeke
Abstract: Embodiments of the present disclosure relate to a system, a software application, and a method of a lithography process to update one or more of a mask pattern, maskless lithography device parameters, lithography process parameters utilizing a file readable by each of the components of a lithography environment. The file readable by each of the components of a lithography environment stores and shares textual data and facilitates communication between of the components of a lithography environment such that the mask pattern corresponds to a pattern to be written is updated, the maskless lithography device of the lithography environment is calibrated, and process parameters of the lithography process are corrected for accurate writing of the mask pattern on successive substrates.
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公开(公告)号：US10429744B2
公开(公告)日：2019-10-01
申请号：US16016162
申请日：2018-06-22
Applicant: Applied Materials, Inc.
Inventor： Tamer Coskun , Hwan J. Jeong
Abstract: Methods and apparatuses are provided that determine an offset between actual feature/mark locations and the designed feature/mark locations in a maskless lithography system. For example, in one embodiment, a method is provided that includes opening a camera shutter in a maskless lithography system. Light is directed from a configuration of non-adjacent mirrors in a mirror array towards a first substrate layer. An image of the first substrate layer on a camera is captured and accumulated. Light is directed and images are captured repeatedly using different configurations of non-adjacent mirrors to cover an entire field-of-view (FOV) of the camera on the first substrate layer. Thereafter, the camera shutter is closed and the accumulated image is stored in memory.
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公开(公告)号：US10133193B2
公开(公告)日：2018-11-20
申请号：US15644284
申请日：2017-07-07
Applicant: Applied Materials, Inc.
Inventor： Tamer Coskun , Hwan J. Jeong
IPC: G03F7/20
Abstract: Embodiments disclosed herein generally relate to adjusting exposure parameters of a substrate in response to an overlay error. The method includes partitioning the substrate into one or more sections. Each section corresponds to an image projection system. A total overlay error of a first layer deposited on the substrate is determined. For each section, a sectional overlay error is calculated. For each overlap area, in which two or more sections overlap, an average overlay error is calculated. The exposure parameters are adjusted in response to the total overlay error.
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4.发明授权公开(公告)号：US11934762B2
公开(公告)日：2024-03-19
申请号：US17396453
申请日：2021-08-06
Applicant: Applied Materials, Inc.
Inventor： Tamer Coskun , Aidyn Kemeldinov , Chung-Shin Kang , Uwe Hollerbach , Thomas L Laidig
IPC: G06F30/39 , G06F30/392 , G06N20/00 , H01L21/68
CPC classification number: G06F30/392 , G06N20/00 , H01L21/68
Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.
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公开(公告)号：US20250076768A1
公开(公告)日：2025-03-06
申请号：US18555896
申请日：2023-04-17
Applicant: Applied Materials, Inc.
Inventor： Zhongchuan Zhang , Rendong Lin , Meenaradchagan Vishnu , Tamer Coskun , Ulrich Mueller , Thomas L. Laidig , Jang Fung Chen
Abstract: Embodiments of the disclosure relate to digital lithography system and related methods, the system including at least one light source configured to emit a light beam onto a substrate via a lens, at least one image sensor, configured to detect a reflected light beam from the substrate via the lens, at least one motor configured to move the lens to focus the light beam onto the substrate, and a controller in communication with the at least one light source, the at least one image sensor and the at least one motor, wherein the controller is to actuate the at least one motor to move the lens in response to at least one signal from the at least one image sensor.
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Patent Agency Ranking
公开(公告)号：US10599055B1
公开(公告)日：2020-03-24
申请号：US16192591
申请日：2018-11-15
Applicant: Applied Materials, Inc.
Inventor： Tamer Coskun , Rudolf C. Brunner
Abstract: A method of aligning a plate containing a substrate is disclosed wherein multiple cameras with distinct fields of view are aligned with mark cells that are within the field of view of each of the multiple cameras.
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公开(公告)号：US20180373161A1
公开(公告)日：2018-12-27
申请号：US16016162
申请日：2018-06-22
Applicant: Applied Materials, Inc.
Inventor： Tamer Coskun , Hwan J. Jeong
CPC classification number: G03F7/70483 , G03F7/70291 , G03F9/7088 , G06T1/0014 , G06T7/0004 , G06T7/33 , G06T2200/32 , G06T2207/10016 , G06T2207/20221 , G06T2207/30148 , H04N5/2353
Abstract: Methods and apparatuses are provided that determine an offset between actual feature/mark locations and the designed feature/mark locations in a maskless lithography system. For example, in one embodiment, a method is provided that includes opening a camera shutter in a maskless lithography system. Light is directed from a configuration of non-adjacent mirrors in a mirror array towards a first substrate layer. An image of the first substrate layer on a camera is captured and accumulated. Light is directed and images are captured repeatedly using different configurations of non-adjacent mirrors to cover an entire field-of-view (FOV) of the camera on the first substrate layer. Thereafter, the camera shutter is closed and the accumulated image is stored in memory.
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公开(公告)号：US10115687B2
公开(公告)日：2018-10-30
申请号：US15424366
申请日：2017-02-03
Applicant: Applied Materials, Inc.
Inventor： Tamer Coskun , Jang Fung Chen
Abstract: In one embodiment of the invention, a method for correcting a pattern placement on a substrate is disclosed. The method begins by detecting three reference points for a substrate. A plurality of sets of three die location points are detected, each set indicative of an orientation of a die structure, the plurality of sets include a first set associated with a first dies and a second set associated with a second die. A local transformation is calculated for the orientation of the first die and the second on the substrate. Three orientation points are selected from the plurality of sets of three die location points wherein the orientation points are not set members of the same die. A first global orientation of the substrate is calculated from the selected three points from the set of points and the first global transformation and the local transformation for the substrate are stored.
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9.发明授权公开(公告)号：US12242789B2
公开(公告)日：2025-03-04
申请号：US18439287
申请日：2024-02-12
Applicant: Applied Materials, Inc.
Inventor： Tamer Coskun , Aidyn Kemeldinov , Chung-Shin Kang , Uwe Hollerbach , Thomas L. Laidig
IPC: G06F30/39 , G06F30/392 , G06N20/00 , H01L21/68
Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.
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公开(公告)号：US10809637B1
公开(公告)日：2020-10-20
申请号：US16426458
申请日：2019-05-30
Applicant: Applied Materials, Inc.
Inventor： Tamer Coskun
Abstract: In one embodiment, a method for creating a forecasting model for a multiple-imaging unit DLT is disclosed. A stage of the DLT is positioned so that a set of alignment marks provided on a substrate are placed under a set of the DLT's eyes. For each alignment mark in the set, a first image is acquired using a camera coupled to the eye above it at a first time, and a first position of the alignment mark is obtained within the camera's FOV from the first image, to determine a first measured position. One or more additional images of the alignment mark are subsequently obtained at subsequent times, and one or more corresponding subsequent measured positions are determined. Differences between sequential ones of the measured positions are respectively calculated, a forecasting model to correct for eye center drift of the set of eyes is created, and corrections digitally applied.
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