公开(公告)号：US11195923B2

公开(公告)日：2021-12-07

申请号：US16678526

申请日：2019-11-08

Applicant: Applied Materials, Inc.

Inventor： Gaurav Thareja ,  Xuebin Li ,  Abhishek Dube ,  Yi-Chiau Huang ,  Tushar Vidyadhar Mandrekar ,  Andy Lo ,  Patricia M. Liu ,  Sanjay Natarajan ,  Saurabh Chopra

IPC: H01L21/44 ,  H01L29/40 ,  H01L29/417 ,  H01L21/02 ,  H01L29/08 ,  H01L21/67 ,  H01L29/66 ,  H01L21/285 ,  H01L29/45

Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.