公开(公告)号：US12015042B2

公开(公告)日：2024-06-18

申请号：US16797807

申请日：2020-02-21

Applicant: Applied Materials, Inc.

Inventor： Papo Chen ,  Schubert Chu ,  Errol Antonio C Sanchez ,  John Timothy Boland ,  Zhiyuan Ye ,  Lori Washington ,  Xianzhi Tao ,  Yi-Chiau Huang ,  Chen-Ying Wu

IPC: H01L27/146 ,  H01L31/18

CPC classification number: H01L27/14636 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/1892

Abstract: A method of fabricating a semiconductor device includes forming an interconnect structure over a front side of a sensor substrate, thinning the sensor substrate from a back side of the sensor substrate, etching trenches into the sensor substrate, pre-cleaning an exposed surface of the sensor substrate, epitaxially growing a charge layer directly on the pre-cleaned exposed surface of the sensor substrate, and forming isolation structures within the etched trenches.

公开(公告)号：US20220375753A1

公开(公告)日：2022-11-24

申请号：US17882177

申请日：2022-08-05

Applicant: Applied Materials, Inc.

Inventor： Wolfgang Aderhold ,  Yi-Chiau Huang ,  Wei Liu ,  Benjamin Colombeau ,  Abhilash Mayur

IPC: H01L21/225 ,  H01L21/324

Abstract: A method of selectively and conformally doping semiconductor materials is disclosed. Some embodiments utilize a conformal dopant film deposited selectively on semiconductor materials by thermal decomposition. Some embodiments relate to doping non-line of sight surfaces. Some embodiments relate to methods for forming a highly doped crystalline semiconductor layer.

公开(公告)号：US20220230877A1

公开(公告)日：2022-07-21

申请号：US17577113

申请日：2022-01-17

Applicant: Applied Materials, Inc.

Inventor： Chen-Ying Wu ,  Yi-Chiau Huang

IPC: H01L21/02

Abstract: Methods for depositing a silicon germanium tin boron (SiGeSn:B) film on a substrate are described. The method comprises exposing a substrate to a precursor mixture comprising a boron precursor, a silicon precursor, a germanium precursor, and a tin precursor to form a boron silicon germanium tin (SiGeSn:B) film on the substrate.

公开(公告)号：US11195923B2

公开(公告)日：2021-12-07

申请号：US16678526

申请日：2019-11-08

Applicant: Applied Materials, Inc.

Inventor： Gaurav Thareja ,  Xuebin Li ,  Abhishek Dube ,  Yi-Chiau Huang ,  Tushar Vidyadhar Mandrekar ,  Andy Lo ,  Patricia M. Liu ,  Sanjay Natarajan ,  Saurabh Chopra

IPC: H01L21/44 ,  H01L29/40 ,  H01L29/417 ,  H01L21/02 ,  H01L29/08 ,  H01L21/67 ,  H01L29/66 ,  H01L21/285 ,  H01L29/45

Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.

公开(公告)号：US20200051818A1

公开(公告)日：2020-02-13

申请号：US16536600

申请日：2019-08-09

Applicant: Applied Materials, Inc.

Inventor： Wolfgang Aderhold ,  Yi-Chiau Huang ,  Wei Liu ,  Benjamin Colombeau ,  Abhilash Mayur

IPC: H01L21/225 ,  H01L21/324

Abstract: A method of selectively and conformally doping semiconductor materials is disclosed. Some embodiments utilize a conformal dopant film deposited selectively on semiconductor materials by thermal decomposition. Some embodiments relate to doping non-line of sight surfaces. Some embodiments relate to methods for forming a highly doped crystalline semiconductor layer.

公开(公告)号：US11843033B2

公开(公告)日：2023-12-12

申请号：US17231087

申请日：2021-04-15

Applicant: Applied Materials, Inc.

Inventor： Chen-Ying Wu ,  Abhishek Dube ,  Yi-Chiau Huang

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/167 ,  H01L21/02 ,  H01L21/225 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L21/0262 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/2252 ,  H01L29/167 ,  H01L29/6675 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A method for the selective formation of epitaxial layers is described herein. In the method, epitaxial layers are deposited to form source and drain regions around a horizontal gate all around (hGAA structure). The method includes co-flowing a combination of chlorinated silicon containing precursors, antimony containing precursors, and n-type dopant precursors. The resulting source and drain regions are selectively grown from crystalline nanosheets or nanowires of the hGAA structure over the non-crystalline gate structure and dielectric layers. The source and drain regions are predominantly grown in a direction.

公开(公告)号：US11791158B2

公开(公告)日：2023-10-17

申请号：US17577113

申请日：2022-01-17

Applicant: Applied Materials, Inc.

Inventor： Chen-Ying Wu ,  Yi-Chiau Huang

IPC: H01L21/02

CPC classification number: H01L21/02535 ,  H01L21/02532 ,  H01L21/02579

Abstract: Methods for depositing a silicon germanium tin boron (SiGeSn:B) film on a substrate are described. The method comprises exposing a substrate to a precursor mixture comprising a boron precursor, a silicon precursor, a germanium precursor, and a tin precursor to form a boron silicon germanium tin (SiGeSn:B) film on the substrate.

公开(公告)号：US11018003B2

公开(公告)日：2021-05-25

申请号：US16513301

申请日：2019-07-16

Applicant: Applied Materials, Inc.

Inventor： Yi-Chiau Huang ,  Hua Chung

IPC: H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: In an embodiment, a method of selectively depositing a silicon germanium material on a substrate is provided. The method includes positioning the substrate within a substrate processing chamber, the substrate having a dielectric material and a silicon containing single crystal thereon; maintaining the substrate at a temperature of about 450° C. or less; exposing the substrate to a process gas comprising: a silicon source gas, a germanium source gas, an etchant gas, a carrier gas, and at least one dopant source gas; and epitaxially and selectively depositing a first silicon germanium material on the substrate.

公开(公告)号：US09299560B2

公开(公告)日：2016-03-29

申请号：US13736504

申请日：2013-01-08

Applicant: APPLIED MATERIALS, INC.

Inventor： Errol Antonio C. Sanchez ,  Yi-Chiau Huang ,  Xinyu Bao

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/3065

CPC classification number: H01L21/0254 ,  H01L21/02636 ,  H01L21/28525 ,  H01L21/28556 ,  H01L21/3065

Abstract: Methods for depositing a group III-V layer on a substrate are disclosed herein. In some embodiments a method includes depositing a first layer comprising at least one of a first Group III element or a first Group V element on a silicon-containing surface oriented in a direction at a first temperature ranging from about 300 to about 400 degrees Celsius; and depositing a second layer comprising second Group III element and a second Group V element atop the first layer at a second temperature ranging from about 300 to about 600 degrees Celsius.

Abstract translation: 本文公开了在基板上沉积III-V族层的方法。 在一些实施方案中，一种方法包括在第一温度范围为约300至约400°的范围内沉积包含第一III族元素或第一V族元素中的至少一种的第一层在位于<111> 摄氏度 以及在约300至约600摄氏度的第二温度下沉积包含第二层第二组元素和第二组V元素的第二层。

公开(公告)号：US09177815B2

公开(公告)日：2015-11-03

申请号：US13886924

申请日：2013-05-03

Applicant: APPLIED MATERIALS, INC.

Inventor： Yi-Chiau Huang ,  Gregory Menk ,  Errol Antonio C. Sanchez ,  Bingxi Wood

IPC: H01L21/20 ,  H01L21/306 ,  H01L21/321 ,  H01L29/66

CPC classification number: H01L21/30625 ,  H01L21/3212 ,  H01L29/66795

Abstract: Methods for chemical mechanical planarization of patterned wafers are provided herein. In some embodiments, methods of processing a substrate having a first surface and a plurality of recesses disposed within the first surface may include: depositing a first material into the plurality of recesses to predominantly fill the plurality of recesses with the first material; depositing a second material different from the first material into the plurality of recesses and atop the substrate to fill the plurality of recesses and to form a layer atop the first surface; and planarizing the second material using a first slurry in a chemical mechanical polishing tool until the first surface is reached. In some embodiments, a second slurry, different than the first slurry, is used to planarize the substrate to a first level.

Abstract translation: 本文提供了图案化晶片的化学机械平面化方法。 在一些实施例中，处理具有设置在第一表面内的第一表面和多个凹槽的基底的方法可以包括：将第一材料沉积到多个凹部中，以主要用第一材料填充多个凹部; 将不同于所述第一材料的第二材料沉积到所述多个凹部中并且在所述基板的顶部上以填充所述多个凹部并且在所述第一表面的顶部上形成层; 以及使用化学机械抛光工具中的第一浆料平坦化所述第二材料，直到达到所述第一表面。 在一些实施方案中，使用与第一浆料不同的第二浆料将基材平面化至第一层。