公开(公告)号：US09065610B2

公开(公告)日：2015-06-23

申请号：US13865843

申请日：2013-04-18

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda Azenkot ,  Timothy P. Walker

IPC: H03D3/24 ,  H04L25/49 ,  H04L1/00 ,  H03L7/081 ,  H04J3/07

CPC classification number: H04L1/004 ,  H03L1/00 ,  H03L7/081 ,  H03L7/107 ,  H03L2207/50 ,  H04J3/076

Abstract: Systems and methods for smoothing jitter generated by byte stuffing. A frequency synthesizer comprises a smoothing logic coupled with a PLL. The smoothing logic is configured to modify a phase error signal generated by a phase frequency detector into a distributed phase error signal that spread over multiple clock cycles. The distributed phase error signal is used to drive a DCO. The smoothing logic may comprise a ramping logic operable to generate a series of ramping values to substitute a phase difference in the phase error signal. The phase difference may correspond to a stuffing byte.

Abstract translation: 用于平滑由字节填充产生的抖动的系统和方法。 频率合成器包括与PLL耦合的平滑逻辑。 平滑逻辑被配置为将由相位频率检测器产生的相位误差信号修改成在多个时钟周期上分布的分布相位误差信号。 分布相位误差信号用于驱动DCO。 平滑逻辑可以包括斜坡逻​​辑，其可操作以产生一系列斜坡值来代替相位误差信号中的相位差。 相位差可对应于填充字节。

公开(公告)号：US09008255B1

公开(公告)日：2015-04-14

申请号：US14061307

申请日：2013-10-23

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda Azenkot ,  Timothy P. Walker

IPC: H04L7/033

CPC classification number: H03L7/093 ,  H04J3/07

Abstract: Systems and methods for efficient jitter mitigation or removal from a gapped signal. A phase mitigation module is employed to generate discrete correction values for modifying phase error signals detected between a gapped signal and a feedback signal of the PLL. The correction values can be digitally subtracted from the output of a phase frequency detector associated with the PLL. The sequence of correction values can be determined based on phase frequency differences between the input signal and a targeted feedback signal that is free of jitter and has a period equal to an average period of the input signal. An average of the correction values is substantially equal to zero, and an average of the modified phase error signal is substantially equal to zero.

Abstract translation: 用于有效抖动缓解或从间隙信号中移除的系统和方法。 使用相位缓解模块来产生离散校正值，用于修改在有效信号和PLL的反馈信号之间检测的相位误差信号。 可以从与PLL相关联的相位频率检测器的输出中数字地减去校正值。 校正值的顺序可以基于输入信号和无抖动的目标反馈信号之间的相位差，并且具有等于输入信号的平均周期的周期来确定。 校正值的平均值基本上等于零，并且修正的相位误差信号的平均值基本上等于零。

公开(公告)号：US08816730B1

公开(公告)日：2014-08-26

申请号：US13846311

申请日：2013-03-18

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda Azenkot ,  Michael Grosner ,  Timothy P. Walker

IPC: H03L7/06

CPC classification number: H03L7/06

Abstract: Systems and methods for frequency synthesis using a gapper. A frequency synthesizer may comprise a gapper, a first integer divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the first integer divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.

Abstract translation: 使用缝隙器进行频率合成的系统和方法。 频率合成器可以包括间隔器，第一整数除法器和锁相环（PLL）。 当输出信号的频率意图大于相应的输入信号时，由第一整数除法器可以通过间隙借用一个因子，以便产生一个大于1的有理分频比G，以使分频器能够 通过G执行除法。PLL能够将从第一整数分频器输出的有间隙信号相乘并衰减来自有间隙信号的抖动。

公开(公告)号：US09281825B2

公开(公告)日：2016-03-08

申请号：US14469456

申请日：2014-08-26

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda Azenkot ,  Michael Grosner ,  Timothy P. Walker

IPC: H03L7/06

CPC classification number: H03L7/06

Abstract: Systems and methods for frequency synthesis using a gapper and a multi-modulus divider. A frequency synthesizer may comprise a gapper, a multi-modulus divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.

Abstract translation: 使用间隙和多模式分频器进行频率合成的系统和方法。 频率合成器可以包括间隔器，多模式分频器和锁相环（PLL）。 当输出信号的频率意图大于相应的输入信号时，可以由分频器借由分频器的因子，以产生大于1的有理分频比G，以使分频器能够执行 由G.的分频。PLL能够乘以来自第一整数分频器的有间隙信号输出，并从有间隙信号衰减抖动。

公开(公告)号：US20150110233A1

公开(公告)日：2015-04-23

申请号：US14061307

申请日：2013-10-23

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda AZENKOT ,  Timothy P. Walker

IPC: H04L7/033

CPC classification number: H03L7/093 ,  H04J3/07

Abstract: Systems and methods for efficient jitter mitigation or removal from a gapped signal. A phase mitigation module is employed to generate discrete correction values for modifying phase error signals detected between a gapped signal and a feedback signal of the PLL. The correction values can be digitally subtracted from the output of a phase frequency detector associated with the PLL. The sequence of correction values can be determined based on phase frequency differences between the input signal and a targeted feedback signal that is free of jitter and has a period equal to an average period of the input signal. An average of the correction values is substantially equal to zero, and an average of the modified phase error signal is substantially equal to zero.

Abstract translation: 用于有效抖动缓解或从间隙信号中移除的系统和方法。 使用相位缓解模块来产生离散校正值，用于修改在有效信号和PLL的反馈信号之间检测的相位误差信号。 可以从与PLL相关联的相位频率检测器的输出中数字地减去校正值。 校正值的顺序可以基于输入信号和无抖动的目标反馈信号之间的相位差，并且具有等于输入信号的平均周期的周期来确定。 校正值的平均值基本上等于零，并且修正的相位误差信号的平均值基本上等于零。

公开(公告)号：US09369135B2

公开(公告)日：2016-06-14

申请号：US13846171

申请日：2013-03-18

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda Azenkot ,  Michael Grosner ,  Timothy P. Walker

IPC: H03B19/00 ,  H03L7/06

CPC classification number: H03L7/06

Abstract: Systems and methods for generating gapped signals comprising a Delta Sigma Modulator (DSM) configured to generate gapping control signals used to control gap removal rates of an associated gapping unit. The DSM is configured to generate a gapping control signal based on a value of an overflow resulted from performing adding a first number with a remainder of a stored value modulo a second number. The gap removal rates as well as the gap removal resolutions can be adjusted by selecting appropriate values of the first number, the stored value, and the second number. The gapping resolution can be a portion of a pulse. The first number and the second number may be derived from an intended frequency ratio between a gapped signal and a corresponding input signal. The gapping unit may comprise a gapping circuit or a multi-modulus divider.

Abstract translation: 用于产生有间隙信号的系统和方法包括配置成产生用于控制相关间隙单元的间隙去除速率的间隙控制信号的ΔΣ调制器（DSM）。 DSM被配置为基于通过执行将具有第二数量的存储值的剩余部分的第一数字相加的溢出的值来生成间隙控制信号。 可以通过选择第一个数字，存储值和第二个数字的适当值来调整间隙去除率以及间隙去除分辨率。 间隙分辨率可以是脉冲的一部分。 第一数字和第二数字可以从有间隙信号和对应的输入信号之间的预期频率比率导出。 间隙单元可以包括间隙电路或多模式分配器。