High speed bus system that incorporates uni-directional point-to-point buses
    2.
    发明授权
    High speed bus system that incorporates uni-directional point-to-point buses 失效
    采用单向点对点总线的高速总线系统

    公开(公告)号:US06928500B1

    公开(公告)日:2005-08-09

    申请号:US08883118

    申请日:1997-06-26

    摘要: A high speed bus system for use in a shared memory system that allows for the high speed transmissions of commands and data between a number of processors and a memory array of a multi-processor, shared memory system, with the high speed bus system including a central unit and a series of uni-directional buses that connect between the plurality of processors and shared memory, with the central unit including arbitration logic and a series of multiplexers to determine which CPUs are granted access to shared buses, scheduling logic that works with the arbitration logic and multiplexers to determine which CPUs are granted access to the shared buses, and port logic for combining the CPU transmissions and determining if such transmissions are valid.

    摘要翻译: 一种用于共享存储器系统的高速总线系统,其允许多个处理器与多处理器共享存储器系统的存储器阵列之间的命令和数据的高速传输,其中高速总线系统包括 中央单元和连接在多个处理器和共享存储器之间的一系列单向总线,中央单元包括仲裁逻辑和一系列多路复用器,以确定哪些CPU被授权访问共享总线,调度逻辑与 仲裁逻辑和多路复用器,以确定哪些CPU被授权访问共享总线,以及端口逻辑,用于组合CPU传输并确定这些传输是否有效。