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    Method and Apparatus for Color Decision Metadata Generation
    1.
    发明申请
    Method and Apparatus for Color Decision Metadata Generation 有权
    用于颜色决策元数据生成的方法和装置

    公开(公告)号：US20070268411A1

    公开(公告)日：2007-11-22

    申请号：US11663246

    申请日：2005-09-29

    Applicant: Eric Rehm ,  Joshua Pines ,  Pierre Ollivier ,  Jan Rooy ,  David Bancroft

    Inventor： Eric Rehm ,  Joshua Pines ,  Pierre Ollivier ,  Jan Rooy ,  David Bancroft

    IPC: H04N9/64

    CPC classification number: H04N9/64 ,  G11B27/034 ,  H04N1/60 ,  H04N19/102 ,  H04N19/17 ,  H04N19/46

    Abstract: A method presents metadata that is used for determining the color correction processes to be performed on image data representing a sequence of moving images (705). Instructions in the metadata controls how many color corrections are to be performed and when such operations occur. The image data is then subjected to the specified color correction operations that are performed at specified times and in a determined order (710). The image data is then rendered as a series of images (715) by a rendering device. Optionally, different regions of the image data may be subjected to different color correction operations.

    Abstract translation: 一种方法提供用于确定对表示运动图像序列的图像数据执行的颜色校正处理的元数据（705）。 元数据中的说明控制要执行多少种颜色校正以及何时执行此类操作。 然后对图像数据进行指定的颜色校正操作，其在指定的时间和确定的顺序执行（710）。 然后，图像数据由渲染装置呈现为一系列图像（715）。 可选地，可以对图像数据的不同区域进行不同的颜色校正操作。

    Data transfer engine of a processor having a plurality of modules
    4.
    发明授权
    Data transfer engine of a processor having a plurality of modules 有权
    具有多个模块的处理器的数据传输引擎

    公开(公告)号：US07051123B1

    公开(公告)日：2006-05-23

    申请号：US09710192

    申请日：2000-11-10

    Applicant: David Baker ,  Christopher Basoglu ,  Benjamin Cutler ,  Gregorio Gervasio ,  Woobin Lee ,  Yatin Mundkur ,  Toru Nojiri ,  John O'Donnell ,  Ashok Raman ,  Eric Rehm ,  Radhika Thekkath

    Inventor： David Baker ,  Christopher Basoglu ,  Benjamin Cutler ,  Gregorio Gervasio ,  Woobin Lee ,  Yatin Mundkur ,  Toru Nojiri ,  John O'Donnell ,  Ashok Raman ,  Eric Rehm ,  Radhika Thekkath

    IPC: G06F3/00

    CPC classification number: G06F13/30 ,  G06F13/1605

    Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus.An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.

    Abstract translation: 在具有处理器，主存储器和多个I / O设备的多个模块的信息处理系统中，用于在处理器，主存储器和I / O设备之间执行数据传送操作的数据传送开关包括请求总线 其具有用于从多个模块中的每一个接收读取和写入请求的请求总线仲裁器。 处理器存储器总线被配置为从包括处理器的预定数量的模块接收地址和数据信息。 处理器存储器总线具有用于从耦合到处理器存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。 内部存储器总线被配置为从包括存储器和I / O设备的预定数量的模块接收地址和数据信息。 内部存储器总线具有用于从耦合到内部存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。 收发器系统耦合到处理器存储器总线和内部存储器总线，用于在处理器存储器总线和内部存储器总线之间传送数据。

    Data streamer
    5.
    发明授权
    Data streamer 有权
    数据流

    公开(公告)号：US07548996B2

    公开(公告)日：2009-06-16

    申请号：US11224738

    申请日：2005-09-12

    Applicant: David Baker ,  Christopher Basoglu ,  Benjamin Cutler ,  Gregorio Gervasio ,  Woobin Lee ,  Yatin Mundkur ,  Toru Nojiri ,  John O'Donnell ,  John Poole, legal representative ,  Ashok Raman ,  Eric Rehm ,  Radhika Thekkath

    Inventor： David Poole

    IPC: G06F13/28

    CPC classification number: G06F13/30 ,  G06F13/1605

    Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus.An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.

    Abstract translation: 在具有处理器，主存储器和多个I / O设备的多个模块的信息处理系统中，用于在处理器，主存储器和I / O设备之间执行数据传送操作的数据传送开关包括请求总线 其具有用于从多个模块中的每一个接收读取和写入请求的请求总线仲裁器。 处理器存储器总线被配置为从包括处理器的预定数量的模块接收地址和数据信息。 处理器存储器总线具有用于从耦合到处理器存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。 内部存储器总线被配置为从包括存储器和I / O设备的预定数量的模块接收地址和数据信息。 内部存储器总线具有用于从耦合到内部存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。 收发器系统耦合到处理器存储器总线和内部存储器总线，用于在处理器存储器总线和内部存储器总线之间传送数据。

    SYSTEM AND PROCESS FOR SEARCHING A NETWORK
    6.
    发明申请
    SYSTEM AND PROCESS FOR SEARCHING A NETWORK 审中-公开
    用于搜索网络的系统和过程

    公开(公告)号：US20070130131A1

    公开(公告)日：2007-06-07

    申请号：US11672139

    申请日：2007-02-07

    Applicant: Charles Porter ,  Jonathan Reich Hold ,  Eric Rehm

    Inventor： Charles Porter ,  Jonathan Reich Hold ,  Eric Rehm

    IPC: G06F17/30

    CPC classification number: G06F16/27 ,  G06F16/41 ,  G06F16/4387 ,  G06F16/48 ,  G06F16/907 ,  G06F16/951 ,  G06F16/9535 ,  G06F16/955 ,  G06F17/2705 ,  Y10S707/913 ,  Y10S707/923 ,  Y10S707/959 ,  Y10S707/99933 ,  Y10S707/99934 ,  Y10S707/99935 ,  Y10S707/99943 ,  Y10S707/99945 ,  Y10S707/99948

    Abstract: A system for searching a network for network based content related to a search query, such as multimedia and streaming media, includes an adapter for formatting the search query, a first database containing previous search results and a second database for storing currently returnable metadata, a search processor, and at least one search engine kernel comprising a search engine inherent database. The search engine coordinates searching of the first database and the second database, and provides the formatted search query to the search engine kernel. The search processor also provides and receives search results to and from the first database and the second database, and provides search results to the adapter. The system stores a predetermined amount of previous search results in the first database, such that search results for a current search are retrieved from the database, avoiding a search through search engine kernel comprising searchable metadata.

    Abstract translation: 一种用于搜索网络以搜索诸如多媒体和流媒体之类的搜索查询的基于网络的内容的系统，包括用于格式化搜索查询的适配器，包含先前搜索结果的第一数据库和用于存储当前可返回元数据的第二数据库， 搜索处理器以及包括搜索引擎固有数据库的至少一个搜索引擎内核。 搜索引擎协调第一数据库和第二数据库的搜索，并将格式化的搜索查询提供给搜索引擎内核。 搜索处理器还向第一数据库和第二数据库提供和接收搜索结果，并向适配器提供搜索结果。 系统将预定量的先前搜索结果存储在第一数据库中，使得从数据库检索当前搜索的搜索结果，避免通过包括可搜索元数据的搜索引擎内核进行搜索。

    Data streamer
    8.
    发明授权
    Data streamer 有权
    数据流

    公开(公告)号：US06434649B1

    公开(公告)日：2002-08-13

    申请号：US09173297

    申请日：1998-10-14

    Applicant: David Baker ,  Christopher Basoglu ,  Benjamin Cutler ,  Gregorio Gervasio ,  Woobin Lee ,  Yatin Mundkur ,  Toru Nojiri ,  John O'Donnell ,  David Poole ,  Ashok Raman ,  Eric Rehm ,  Radhika Thekkath

    Inventor： David Baker ,  Christopher Basoglu ,  Benjamin Cutler ,  Gregorio Gervasio ,  Woobin Lee ,  Yatin Mundkur ,  Toru Nojiri ,  John O'Donnell ,  David Poole ,  Ashok Raman ,  Eric Rehm ,  Radhika Thekkath

    IPC: G06F1300

    CPC classification number: G06F13/30 ,  G06F13/1605

    Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.

    Abstract translation: 在具有处理器，主存储器和多个I / O设备的多个模块的信息处理系统中，用于在处理器，主存储器和I / O设备之间执行数据传送操作的数据传送开关包括请求总线 其具有用于从多个模块中的每一个接收读取和写入请求的请求总线仲裁器。 处理器存储器总线被配置为从包括处理器的预定数量的模块接收地址和数据信息。 处理器存储器总线具有用于从耦合到处理器存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。内部存储器总线被配置为从预定数量接收地址和数据信息 的模块，包括内存和I / O设备。 内部存储器总线具有用于从耦合到内部存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。 收发器系统耦合到处理器存储器总线和内部存储器总线，用于在处理器存储器总线和内部存储器总线之间传送数据。

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