公开(公告)号：US07668997B2

公开(公告)日：2010-02-23

申请号：US11152213

申请日：2005-06-14

申请人： Raj Ramanujan ,  James B. Keller ,  William A. Samaras ,  John DeRosa ,  Robert E. Stewart

发明人： Raj Ramanujan ,  James B. Keller ,  William A. Samaras ,  John DeRosa ,  Robert E. Stewart

IPC分类号： G06F12/00

CPC分类号： H04L12/403 ,  G06F15/167 ,  G06F15/173 ,  H04L12/4625

摘要： An apparatus comprises a plurality of ports wherein each port is adapted to couple to a device. At least one port connects by way of first and second unidirectional, point-to-point communication links with a device. The first unidirectional, point-to-point communication link transfers data from the device to the central logic unit and the second unidirectional, point-to-point communication link transfers data from the central logic unit to the device.

摘要翻译： 一种装置包括多个端口，其中每个端口适于耦合到设备。 至少一个端口通过与设备的第一和第二单向，点对点通信链路连接。 第一单向点对点通信链路将数据从设备传送到中央逻辑单元，第二单向点对点通信链路将数据从中央逻辑单元传送到设备。

公开(公告)号：US06928500B1

公开(公告)日：2005-08-09

申请号：US08883118

申请日：1997-06-26

申请人： Raj Ramanujan ,  James B. Keller ,  William A. Samaras ,  John Derosa ,  Robert E. Stewart

发明人： Raj Ramanujan ,  James B. Keller ,  William A. Samaras ,  John Derosa ,  Robert E. Stewart

IPC分类号： G06F15/167 ,  G06F15/173 ,  H04L12/28 ,  H04L12/403 ,  G06F13/14 ,  G06F13/36

CPC分类号： H04L12/403 ,  G06F15/167 ,  G06F15/173 ,  H04L12/4625

摘要： A high speed bus system for use in a shared memory system that allows for the high speed transmissions of commands and data between a number of processors and a memory array of a multi-processor, shared memory system, with the high speed bus system including a central unit and a series of uni-directional buses that connect between the plurality of processors and shared memory, with the central unit including arbitration logic and a series of multiplexers to determine which CPUs are granted access to shared buses, scheduling logic that works with the arbitration logic and multiplexers to determine which CPUs are granted access to the shared buses, and port logic for combining the CPU transmissions and determining if such transmissions are valid.

摘要翻译： 一种用于共享存储器系统的高速总线系统，其允许多个处理器与多处理器共享存储器系统的存储器阵列之间的命令和数据的高速传输，其中高速总线系统包括 中央单元和连接在多个处理器和共享存储器之间的一系列单向总线，中央单元包括仲裁逻辑和一系列多路复用器，以确定哪些CPU被授权访问共享总线，调度逻辑与 仲裁逻辑和多路复用器，以确定哪些CPU被授权访问共享总线，以及端口逻辑，用于组合CPU传输并确定这些传输是否有效。

公开(公告)号：US5202973A

公开(公告)日：1993-04-13

申请号：US546548

申请日：1990-06-29

申请人： Raj Ramanujan ,  James B. Keller ,  Jay Stickney ,  Steven Ho ,  Paul Lemmon

发明人： Raj Ramanujan ,  James B. Keller ,  Jay Stickney ,  Steven Ho ,  Paul Lemmon

IPC分类号： G06F13/16 ,  G06F13/376

CPC分类号： G06F13/161 ,  G06F13/376

摘要： A system and method for controlling a shared memory bus in a computer of a multi-processor system prevents collisions on the shared bus and ensures that the bus is full at system start-up. Steady state operations are maintained without the need for a queuing mechanism in the system's memory controller and in view of the memory modules of the shared memory having different read access times, with the system and method being implemented in a system that includes a central unit and multiple uni-directional buses that are disposed between a shared memory and a plurality of processors, with the central unit controlling access to, and use of, the shared buses of the system.

摘要翻译： 用于控制多处理器系统的计算机中的共享存储器总线的系统和方法防止共享总线上的冲突，并确保总线在系统启动时已满。 维持稳定状态操作，而不需要系统存储器控制器中的排队机制，并且考虑到具有不同读取访问时间的共享存储器的存储器模块，系统和方法在包括中央单元和 多个单向总线设置在共享存储器和多个处理器之间，中央单元控制对系统的共享总线的访问和使用。

公开(公告)号：US5029076A

公开(公告)日：1991-07-02

申请号：US512571

申请日：1990-04-09

申请人： Robert E. Stewart ,  James B. Keller

发明人： Robert E. Stewart ,  James B. Keller

IPC分类号： G06F13/364 ,  G06F13/40

CPC分类号： G06F13/4072 ,  G06F13/364

摘要： In a data processing system in which a plurality of data processing units or subsystems exchange logic signal groups by means of a system bus, apparatus is provided to allow sufficient time to permit transients on the system bus to decay, thereby increasing the integrity of the data. When the logic signal groups are applied to the system bus via conducting and nonconducting transistors, the presence of a logic signal on the system bus immediately prior to the application of a set of logic signals from a different data processing unit can delay the on-set of conduction of the most recently activated transistors, thereby resulting in transients of long duration. To accommodate these long transient conditions, the application of the new set of logic signals can be delayed until the transients on the system bus have been attenuated. Apparatus is disclosed for prohibiting access to the system bus by any subsystem during the system clock cycle following a subsystem access or by preventing access to the system bus by subsystems determined by the subsystem having access during the prior system clock cycle.

摘要翻译： 在其中多个数据处理单元或子系统通过系统总线交换逻辑信号组的数据处理系统中，提供设备以允许足够的时间来允许系统总线上的瞬变衰减，从而增加数据的完整性 。 当逻辑信号组通过导通和非导体晶体管施加到系统总线时，在应用来自不同数据处理单元的一组逻辑信号之前，系统总线上的逻辑信号的存在可以延迟设定 导致最近激活的晶体管的导通，从而导致长时间的瞬变。 为了适应这些长时间的瞬态条件，可以延迟新的逻辑信号集的应用，直到系统总线上的瞬变被衰减为止。 公开了用于在子系统访问之后的系统时钟周期期间禁止任何子系统访问系统总线的装置，或者通过由在先前系统时钟周期期间具有访问权限的子系统确定的子系统阻止对系统总线的访问。

公开(公告)号：US4755936A

公开(公告)日：1988-07-05

申请号：US823805

申请日：1986-01-29

申请人： Robert E. Stewart ,  Barry J. Flahive ,  James B. Keller

发明人： Robert E. Stewart ,  Barry J. Flahive ,  James B. Keller

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0855

摘要： A cache memory unit is disclosed in which, in response to the application of a write command, the write operation is performed in two system clock cycles. During the first clock cycle, the data signal group is stored in a temporary storage unit while a determination is made if the address signal group associated with the data signal group is present in the cache memory unit. When the address signal group is present, the data signal group is stored in the cache memory unit during the next application of a write command to the cache memory unit. If a read command is applied to the cache memory unit involving the data signal group stored in the temporary storage unit, then this data signal group is transferred to the central processing unit in response to the read command. Instead of performing the storage into the cache memory unit as a result of the next write command, the storage of the data signal in the cache memory unit can occur during any free cycle.

摘要翻译： 公开了一种高速缓冲存储器单元，其中响应于写入命令的应用，在两个系统时钟周期中执行写入操作。 在第一时钟周期期间，数据信号组存储在临时存储单元中，同时确定与数据信号组相关联的地址信号组是否存在于高速缓冲存储器单元中。 当存在地址信号组时，在下一次向高速缓冲存储器单元施加写入命令时，将数据信号组存储在高速缓冲存储器单元中。 如果读取命令被应用于存储在临时存储单元中的数据信号组的高速缓冲存储器单元，则该数据信号组被响应于读取命令传送到中央处理单元。 作为下一个写入命令的结果，代替执行到高速缓冲存储器单元的存储，数据信号在高速缓冲存储器单元中的存储可以在任何空闲周期期间发生。

公开(公告)号：US4858173A

公开(公告)日：1989-08-15

申请号：US823775

申请日：1986-01-29

申请人： Robert E. Stewart ,  Paul J. Natusch ,  Eugene L. Yu ,  James B. Keller

发明人： Robert E. Stewart ,  Paul J. Natusch ,  Eugene L. Yu ,  James B. Keller

IPC分类号： G06F15/16 ,  G06F13/16 ,  G06F13/18 ,  G06F13/364 ,  G06F15/177

CPC分类号： G06F13/364

摘要： In a data processing system in which access to a second unit by a first unit through a system bus is determined by an arbitration unit, when a requesting unit that receives access to the system bus is unable to use that access for interaction with the second unit, a busy signal is provided to the arbitration unit and to the units. The busy signal causes the units to reinstitute a request for access to the system bus when the subsystem had an aborted transaction. The busy signal enforces a delay in the next arbitration for the system bus until a unit, with an aborted transaction as a result of the busy signal, can reassert the request for access signal. Moreover, apparatus can be included with the arbitration unit that permits rearbitrating access to the bus using the priority conditions in effect at the time of the original arbitration.

摘要翻译： 在数据处理系统中，由仲裁单元确定由第一单元通过系统总线访问第二单元的数据处理系统，当接收对系统总线的访问的请求单元不能使用与第二单元交互的访问时 向仲裁单元和单元提供忙信号。 当子系统中止事务时，繁忙的信号导致单元重新建立访问系统总线的请求。 忙信号在系统总线的下一个仲裁中强制执行延迟，直到由于忙信号而导致中止事务的单元可以重新发送接入信号请求。 此外，可以在允许使用在原始仲裁时有效的优先级条件使总线访问总线的仲裁单元中包含设备。

公开(公告)号：US08744602B2

公开(公告)日：2014-06-03

申请号：US13008171

申请日：2011-01-18

申请人： Gurjeet S. Saund ,  James B. Keller ,  Michael Frank

发明人： Gurjeet S. Saund ,  James B. Keller ,  Michael Frank

IPC分类号： G05B11/01 ,  H04W4/00

CPC分类号： H04L49/10

摘要： One or more fabric control circuits may be inserted in a communication fabric to control various aspects of the communications by components in the system. The fabric control circuits may be included on the interface of the components to the communication fabric, for example. Some systems that include a hierarchical communication fabric may also include fabric control circuits that may alternatively or additionally be included. The fabric control circuits may be programmable, and thus may provide the ability to tune the communication fabric to meet performance and/or functionality goals.

摘要翻译： 可以将一个或多个结构控制电路插入到通信结构中，以通过系统中的组件来控制通信的各个方面。 例如，结构控制电路可以包括在组件的接口到通信结构。 包括分级通信结构的一些系统还可以包括可以可选地或另外包括的结构控制电路。 织物控制电路可以是可编程的，因此可以提供调谐通信结构以满足性能和/或功能目标的能力。

公开(公告)号：US20130290681A1

公开(公告)日：2013-10-31

申请号：US13460178

申请日：2012-04-30

申请人： James B. Keller ,  John H. Mylius ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Sandeep Gupta

发明人： James B. Keller ,  John H. Mylius ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Sandeep Gupta

IPC分类号： G06F9/30

CPC分类号： G06F9/30141 ,  G06F1/3234 ,  G06F9/30112 ,  G06F9/384

摘要： A system and method for efficiently reducing the power consumption of register file accesses. A processor is operable to execute instructions with two or more data types, each with an associated size and alignment. Data operands for a first data type use operand sizes equal to an entire width of a physical register within a physical register file. Data operands for a second data type use operand sizes less than an entire width of a physical register. Accesses of the physical register file for operands associated with a non-full-width data type do not access a full width of the physical registers. A given numerical value may be bypassed for the portion of the physical register that is not accessed.

摘要翻译： 一种有效降低寄存器文件访问功耗的系统和方法。 处理器可操作以执行具有两个或多个数据类型的指令，每个数据类型具有相关联的大小和对齐。 第一种数据类型的数据操作数使用等于物理寄存器文件中物理寄存器的整个宽度的操作数大小。 第二种数据类型的数据操作数使用小于物理寄存器整个宽度的操作数大小。 访问与非全宽数据类型相关的操作数的物理寄存器文件不能访问物理寄存器的全部宽度。 对于未访问的物理寄存器的部分，可以忽略给定的数值。

公开(公告)号：US08566526B2

公开(公告)日：2013-10-22

申请号：US13545526

申请日：2012-07-10

申请人： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

发明人： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

IPC分类号： G06F13/00

CPC分类号： G06F3/0631 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/0802 ,  G06F12/0831 ,  G06F12/0848 ,  G06F12/0853 ,  G06F12/0864 ,  G06F12/0877 ,  G06F12/125 ,  G06F2212/1021 ,  G06F2212/2515 ,  G06F2212/282 ,  G06F2212/601 ,  G06F2212/62 ,  Y02D10/13

摘要： In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

公开(公告)号：US20130275720A1

公开(公告)日：2013-10-17

申请号：US13447651

申请日：2012-04-16

申请人： James B. Keller ,  John H. Mylius ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Suparn Vats

发明人： James B. Keller ,  John H. Mylius ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Suparn Vats

IPC分类号： G06F9/30 ,  G06F9/312

CPC分类号： G06F9/30032 ,  G06F9/384

摘要： A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction is eligible for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move instruction to the destination operand of the move instruction. Additionally, the register rename unit marks the given move instruction to prevent it from proceeding in the processor pipeline. Further maintenance of the particular physical register identifier may be done by the register rename unit during commit of the given move instruction.

摘要翻译： 一种用于减少数据移动操作的延迟的系统和方法。 处理器内的寄存器重命名单元确定解码的移动指令是否符合零周期移动操作的资格。 如果是这样，则控制逻辑将与移动指令的源操作数相关联的物理寄存器标识分配给移动指令的目的地操作数。 此外，寄存器重命名单元标记给定的移动指令以防止其在处理器管线中继续进行。 特定物理寄存器标识符的进一步维护可以在给定移动指令的提交期间由寄存器重命名单元完成。