公开(公告)号：US07545177B1

公开(公告)日：2009-06-09

申请号：US11725742

申请日：2007-03-20

申请人： Sean W. Kao ,  Tim Tuan ,  Arifur Rahman

发明人： Sean W. Kao ,  Tim Tuan ,  Arifur Rahman

IPC分类号： H03K19/096

CPC分类号： H03K19/0016

摘要： Leakage current reduction from a logic block is implemented via power gating transistors that exhibit increased gate oxide thickness as compared to the thin-oxide devices of the power gated logic block. Increased gate oxide further allows increased gate to source voltage differences to exist on the power gating devices, which enhances performance and reduces gate leakage even further. Placement of the power gating transistors in proximity to other increased gate oxide devices minimizes area penalties caused by physical design constraints of the semiconductor die.

摘要翻译： 与电源门控逻辑块的薄氧化物器件相比，通过电源门控晶体管实现了从逻辑块的漏电流减小，其表现出增加的栅极氧化物厚度。 增加的栅极氧化物进一步允许在电源门控器件上存在增加的栅极 - 源极电压差，这进一步提高了性能并降低了栅极泄漏。 功率门控晶体管靠近其他增加的栅极氧化物器件的放置最小化由半导体管芯的物理设计约束引起的面积损失。

公开(公告)号：US07490302B1

公开(公告)日：2009-02-10

申请号：US11196179

申请日：2005-08-03

申请人： Arifur Rahman ,  Sean W. Kao ,  Sathaki Das ,  Tim Tuan

发明人： Arifur Rahman ,  Sean W. Kao ,  Sathaki Das ,  Tim Tuan

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F2217/78

摘要： Power-gating circuit resources of an integrated circuit is described. The circuit resources are associated into sets responsive to utilization levels. The associating includes providing a first set of the sets, a first number of the circuit resources in the first set being associated with a first level of utilization. The associating also includes providing a second set of the sets, a second number of the circuit resources in the second set being associated with a second level of utilization. The first number is less than the second number responsive to the first level of utilization being greater than the second level of utilization. The circuit resources of the first set are commonly coupled to a reference voltage level via a first gating circuit. The circuit resources of the second set are commonly gated to the same or a different reference voltage level via a second gating circuit.

摘要翻译： 描述了集成电路的功率选通电路资源。 电路资源与响应于利用水平的集合相关联。 关联包括提供第一组集合，第一组中的电路资源的第一数量与第一级别的利用相关联。 关联还包括提供第二组集合，第二组中的电路资源的第二数量与第二级别的利用相关联。 第一个数字小于响应于第一个利用水平的第二个数字大于第二个利用水平。 第一组的电路资源通常经由第一选通电路耦合到参考电压电平。 第二组的电路资源通常经由第二选通电路门控到相同或不同的参考电压电平。

公开(公告)号：US07477073B1

公开(公告)日：2009-01-13

申请号：US11454316

申请日：2006-06-16

申请人： Tim Tuan ,  Arifur Rahman ,  Satyaki Das ,  Sean W. Kao

发明人： Tim Tuan ,  Arifur Rahman ,  Satyaki Das ,  Sean W. Kao

IPC分类号： H03K19/177 ,  H03K19/0175

CPC分类号： H03K19/17736 ,  H03K19/17784

摘要： A PLD utilizes a heterogeneous architecture to reduce power consumption of its active resources. The PLD's programmable resources are divided into a first partition and a second partition, where the resources of the first partition are optimized for low power consumption and the resources of the second partition are optimized for high performance. Portions of a user design containing non-critical timing paths are mapped to and implemented by the resources of the power-optimized first partition, and portions of the user design containing critical timing paths are mapped to and implemented by the resources of the performance-optimized second partition.

摘要翻译： PLD利用异构架构来降低其活动资源的功耗。 PLD的可编程资源分为第一分区和第二分区，其中第一分区的资源被优化用于低功耗，并且第二分区的资源被优化用于高性能。 包含非关键定时路径的用户设计的部分被映射到由功率优化的第一分区的资源并由其实现，并且包含关键定时路径的用户设计的部分被映射到由性能优化的资源实现 第二分区。

公开(公告)号：US07498835B1

公开(公告)日：2009-03-03

申请号：US11268265

申请日：2005-11-04

申请人： Arifur Rahman ,  Sean W. Kao ,  Tim Tuan ,  Patrick J. Crotty ,  Jinsong Oliver Huang

发明人： Arifur Rahman ,  Sean W. Kao ,  Tim Tuan ,  Patrick J. Crotty ,  Jinsong Oliver Huang

IPC分类号： H03K19/173 ,  G11C5/14

CPC分类号： H03K19/17772 ,  G06F1/3203 ,  G06F1/3287 ,  G11C5/148 ,  H03K19/0016 ,  H03K19/17784 ,  Y02D10/171 ,  Y02D50/20

摘要： A PLD (200) includes a power management unit (PMU 210) that selectively implements one or more different power-reduction techniques in response to power configuration signals (PC). By manipulating the PC signals, the PMU can independently enable/disable various supply voltage circuits (110, 120, 130) that power CLBs (101), IOBs (102), and configuration memory cells (106), can generate a capture signal that causes data stored in storage elements of the CLBs to be captured in configuration memory cells, and/or can switch power terminals of configuration memory cells between voltage supply circuits. Also, the PMU can sequentially apply and remove power from a number of configurable PLD portions in response to the PC signals, wherein each configurable portion may include any number of the PLD's resources.

摘要翻译： PLD（200）包括功率管理单元（PMU 210），其响应于功率配置信号（PC）选择性地实现一个或多个不同的功率降低技术。 通过操纵PC信号，PMU可以独立地启用/禁用为CLB（101），IOB（102）和配置存储器单元（106）供电的各种电源电压电路（110,120,130）可以产生捕获信号， 导致存储在CLB的存储元件中的数据被捕获在配置存储单元中，和/或可以在电压供应电路之间切换配置存储单元的电源端子。 此外，响应于PC信号，PMU可以顺序地从多个可配置PLD部分中施加和去除电力，其中每个可配置部分可以包括任何数量的PLD资源。

公开(公告)号：US07417454B1

公开(公告)日：2008-08-26

申请号：US11210498

申请日：2005-08-24

申请人： Arifur Rahman ,  Tim Tuan ,  Sean W. Kao

发明人： Arifur Rahman ,  Tim Tuan ,  Sean W. Kao

IPC分类号： H03K19/173

CPC分类号： H03K19/17784 ,  H03K17/002 ,  H03K17/693 ,  H03K19/1731 ,  H03K19/17728

摘要： An apparatus is disclosed that may reduce the dynamic power dissipation of a configurable IC device such as an FPGA by reducing the peak-to-peak voltage swing of signals transmitted over the device's interconnect signal lines without including additional level shifter circuits. For some embodiments, existing multiplexing circuit architectures provided within logic resources of various logic blocks of the configurable IC device may be used as level shifter circuits to increase the voltage swing of signals received into the blocks from the interconnect signal lines, and modified multiplexing circuit architectures provided within the logic resources may be used to reduce the voltage swing of signals output from the logic blocks onto the interconnect signal lines.

摘要翻译： 公开了一种可以通过减少在器件的互连信号线上传输的信号的峰 - 峰电压摆幅而不包括额外的电平移位器电路来降低诸如FPGA的可配置IC器件的动态功耗的装置。 对于一些实施例，在可配置IC器件的各种逻辑块的逻辑资源内提供的现有多路复用电路架构可以用作电平移位器电路，以增加从互连信号线接收到块中的信号的电压摆幅，以及修改的多路复用电路架构 提供在逻辑资源内的信号可用于将从逻辑块输出的信号的电压摆幅减小到互连信号线上。

公开(公告)号：US07463056B1

公开(公告)日：2008-12-09

申请号：US11301056

申请日：2005-12-12

申请人： James B. Anderson ,  Sean W. Kao ,  Arifur Rahman

发明人： James B. Anderson ,  Sean W. Kao ,  Arifur Rahman

IPC分类号： H03K19/173

CPC分类号： H03K19/17752 ,  G11C19/00 ,  G11C19/28 ,  H03K19/17728 ,  H03K19/17756 ,  H03K19/1776

摘要： An FPGA system includes a combined shift register and look up table (LUT) forming a shift register LUT (SRL) that provides data write, reset and shift enable on a cell-by-cell basis. The data write and reset can be performed during FPGA operation without requiring a number of frames or columns of configuration memory cells to be reprogrammed, as with conventional SRAM cells. The shift enable provides for synchronization to facilitate the cell-by-cell write and reset.

摘要翻译： FPGA系统包括组合的移位寄存器和查找表（LUT），其形成移位寄存器LUT（SRL），该移位寄存器LUT（SRL）在逐单元的基础上提供数据写入，复位和移位使能。 可以在FPGA操作期间执行数据写入和复位，而不需要像常规SRAM单元那样重新编程多个配置存储单元的帧或列。 移位启用提供同步以便于逐单元写入和复位。

公开(公告)号：US07500060B1

公开(公告)日：2009-03-03

申请号：US11724808

申请日：2007-03-16

申请人： James B. Anderson ,  Sean W. Kao ,  Arifur Rahman

发明人： James B. Anderson ,  Sean W. Kao ,  Arifur Rahman

IPC分类号： G06F12/00

CPC分类号： G06F12/0875 ,  G06F7/785

摘要： A hardware stack (HSTACK) structure using programmable logic can include a look-up table (LUT) random access memory (RAM) circuit and circuitry within the LUT RAM circuit for propagating data upwards and downwards. The hardware structure can be arbitrarily assembled into a larger structure by adding stacks to a top portion, a bottom portion, or a portion between the top portion and the bottom portion. The hardware stack structure can further include a virtual stack (VSTACK) structure coupled to the HSTACK structure within a field programmable gate array (FPGA) fabric. The VSTACK can be arranged in the form of an appended peripheral memory and cache control for virtual extension to an HSTACK address space. The hardware stack structure can further include an auxiliary reset circuit.

摘要翻译： 使用可编程逻辑的硬件堆栈（HSTACK）结构可以包括查找表（LUT）随机存取存储器（RAM）电路和LUT RAM电路内的电路，用于向上和向下传播数据。 硬件结构可以通过向顶部，底部或顶部和底部之间的部分添加堆叠而任意组装成更大的结构。 硬件堆栈结构还可以包括耦合到现场可编程门阵列（FPGA）结构内的HSTACK结构的虚拟堆栈（VSTACK）结构。 VSTACK可以以附加的外围存储器和高速缓存控制的形式排列，以便虚拟扩展到HSTACK地址空间。 硬件堆叠结构还可以包括辅助复位电路。

公开(公告)号：US07368946B1

公开(公告)日：2008-05-06

申请号：US11454315

申请日：2006-06-16

申请人： Arifur Rahman ,  Sean W. Kao

发明人： Arifur Rahman ,  Sean W. Kao

IPC分类号： H03K19/173 ,  G06F7/38

CPC分类号： H03K19/01818 ,  H03K17/005 ,  H03K17/693

摘要： The present invention incorporates level-shifting functions within a multiplexer circuit that may be implemented in IC devices having low and high voltage domains. The multiplexer circuit utilizes pseudo-differential multiplexing architectures and employs level-shifting techniques to convert low-voltage signals received from the low-voltage domain into high-voltage signals more suitable for controlling the propagation of a selected input signal through the pass gates of the multiplexer circuit. For some embodiments, some of the select signals may be decoded to generate a number of decoded select signals that can be used to control the selective routing of signals through the multiplexer.

摘要翻译： 本发明包括可以在具有低和高电压域的IC器件中实现的多路复用器电路内的电平转换功能。 多路复用器电路利用伪差分复用架构，并采用电平转换技术将从低电压域接收的低电压信号转换成更适合于控制所选择的输入信号通过传输门的传输门的高电压信号 多路复用器电路。 对于一些实施例，可以对某些选择信号进行解码以产生可被用于控制通过多路复用器的信号的选择性路由的多个解码选择信号。

公开(公告)号：US07253661B1

公开(公告)日：2007-08-07

申请号：US11145135

申请日：2005-06-03

申请人： Tim Tuan ,  Sean W. Kao

发明人： Tim Tuan ,  Sean W. Kao

IPC分类号： G06F7/38 ,  H03K3/00

CPC分类号： H03K5/135 ,  H03K3/356052

摘要： A configurable latch is implemented using a configurable pulse generator and a level sensitive (LS) latch. The configurable pulse generator produces either a pulse signal that is aligned with the input clock edge, or simply provides the input clock signal to its output in response to a pulse generator control signal. If a pulse signal is provided to the latch, then edge triggered (ET) latch operation is effected within the latch. If, on the other hand, a clock signal is provided to the latch, then LS latch operation is effected within the latch. Thus, configuration of latch operation is established in response to the type of clock signal that is provided to the latch.

摘要翻译： 可配置的锁存器使用可配置的脉冲发生器和电平敏感（LS）锁存器来实现。 可配置脉冲发生器产生与输入时钟边沿对准的脉冲信号，或者响应于脉冲发生器控制信号简单地向输出提供输入时钟信号。 如果向锁存器提供脉冲信号，则在锁存器内实现边沿触发（ET）锁存操作。 另一方面，如果向锁存器提供时钟信号，则在锁存器内进行LS锁存操作。 因此，响应于提供给锁存器的时钟信号的类型，建立锁存操作的配置。