公开(公告)号：US12147566B2

公开(公告)日：2024-11-19

申请号：US17683681

申请日：2022-03-01

Applicant: Arm Limited

Inventor： Remy Pottier ,  Minsheng Lu ,  Arthur Michael Goldberg ,  Christopher Daniel Emmons

IPC: G06F15/16 ,  G06F21/62

Abstract: Provided is a digital/analog signal processing apparatus and method for controlling exposure of personally identifiable information to be transferred from storage in a secure enclave, comprising a memory and an integrated circuit coupled to the memory, configured to: select a data set stored in the storage; individuate personally identifiable information in the data set; determine an individual person's subset of personally identifiable information; extract an identifier for the individual person from the subset; interrogate stored data using the identifier to locate metadata comprising permission to expose the individual person's subset; and responsive to a failure to locate the metadata comprising permission, either: emit a signal seeking the permission; or apply a protective measure to the individual person's subset of individuated personally identifiable information prior to transfer of the data set in a digital/analog signal outside the secure enclave.

公开(公告)号：US11928163B2

公开(公告)日：2024-03-12

申请号：US17669851

申请日：2022-02-11

Applicant: Arm Limited

Inventor： Remy Pottier ,  Minsheng Lu ,  Arthur Michael Goldberg ,  Christopher Daniel Emmons

IPC: G06F16/908 ,  G06F16/901 ,  G06N20/00

CPC classification number: G06F16/908 ,  G06F16/9024 ,  G06N20/00

Abstract: A technique is provided for creating digital memories for a particular person. A data store stores personal data derived from signals gathered from a plurality of sensors that monitor the particular person. Memories creation processing circuitry, responsive to detection of a given event associated with the particular person, performs an augmentation process to generate an augmented given event identifying multiple items of data associated with the given event, including personal data associated with the given event obtained from the data store. The memories creation processing circuitry analyses the multiple items of data identified by the augmented given event in order to generate a given digital memory for the given event. A memories data store stores digital memories generated by the memories creation processing circuitry for the particular person, and memories analysis circuitry determines and maintains associations between the digital memories in the memories data store. Digital twin creation circuitry may then develop cognitive skills via analysis of the digital memories and their associations, for use in assisting the particular person.

公开(公告)号：US09582282B2

公开(公告)日：2017-02-28

申请号：US14333889

申请日：2014-07-17

Applicant: ARM Limited

Inventor： Mitchell Bryan Hayenga ,  Christopher Daniel Emmons

IPC: G06F9/38 ,  G06F12/0862 ,  G06F12/08

CPC classification number: G06F9/3816 ,  G06F9/3802 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/452 ,  G06F2212/6024

Abstract: A data processing apparatus has prefetch circuitry for prefetching cache lines of instructions into an instruction cache. A prefetch lookup table is provided for storing prefetch entries, with each entry corresponding to a region of a memory address space and identifying at least one block of one or more cache lines within the corresponding region from which processing circuitry accessed an instruction on a previous occasion. When the processing circuitry executes an instruction from a new region, the prefetch circuitry looks up the table, and if it stores a prefetch entry for the new region, then the at least one block identified by the corresponding entry is prefetched into the cache.

Abstract translation: 数据处理装置具有用于将高速缓存行指令预取到指令高速缓存中的预取电路。 提供预取查找表用于存储预取条目，其中每个条目对应于存储器地址空间的区域，并且识别处理电路在其中访问了先前场合的指令的相应区域内的一个或多个高速缓存行的至少一个块 。 当处理电路执行来自新区域的指令时，预取电路查找该表，并且如果它存储新区域的预取条目，则由相应条目标识的至少一个块被预取到高速缓存中。